2020-03-10 20:49:27 -04:00
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namespace ARMeilleure.Decoders
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{
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class OpCode32SimdRegElemLong : OpCode32SimdRegElem
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{
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2022-09-13 17:25:37 -04:00
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, false);
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public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, true);
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2020-10-21 08:13:44 -04:00
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2022-09-13 17:25:37 -04:00
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public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
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2020-03-10 20:49:27 -04:00
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{
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Q = false;
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F = false;
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RegisterSize = RegisterSize.Simd64;
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// (Vd & 1) != 0 || Size == 3 are also invalid, but they are checked on encoding.
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if (Size == 0)
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{
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Instruction = InstDescriptor.Undefined;
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}
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}
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}
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}
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