2019-10-13 02:02:07 -04:00
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namespace Ryujinx.Graphics.Gpu.Memory
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{
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// GPU memory manager.
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/// </summary>
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2019-10-13 02:02:07 -04:00
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public class MemoryManager
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{
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private const ulong AddressSpaceSize = 1UL << 40;
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public const ulong BadAddress = ulong.MaxValue;
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private const int PtLvl0Bits = 14;
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private const int PtLvl1Bits = 14;
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2019-10-26 13:50:52 -04:00
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public const int PtPageBits = 12;
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2019-10-13 02:02:07 -04:00
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private const ulong PtLvl0Size = 1UL << PtLvl0Bits;
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private const ulong PtLvl1Size = 1UL << PtLvl1Bits;
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public const ulong PageSize = 1UL << PtPageBits;
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private const ulong PtLvl0Mask = PtLvl0Size - 1;
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private const ulong PtLvl1Mask = PtLvl1Size - 1;
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public const ulong PageMask = PageSize - 1;
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private const int PtLvl0Bit = PtPageBits + PtLvl1Bits;
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private const int PtLvl1Bit = PtPageBits;
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private const ulong PteUnmapped = 0xffffffff_ffffffff;
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private const ulong PteReserved = 0xffffffff_fffffffe;
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private ulong[][] _pageTable;
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Creates a new instance of the GPU memory manager.
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/// </summary>
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2019-10-13 02:02:07 -04:00
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public MemoryManager()
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{
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_pageTable = new ulong[PtLvl0Size][];
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Maps a given range of pages to the specified CPU virtual address.
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/// </summary>
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2020-01-01 10:39:09 -05:00
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/// <remarks>
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/// All addresses and sizes must be page aligned.
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/// </remarks>
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2019-12-30 22:22:58 -05:00
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/// <param name="pa">CPU virtual address to map into</param>
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/// <param name="va">GPU virtual address to be mapped</param>
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/// <param name="size">Size in bytes of the mapping</param>
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2019-12-30 23:46:57 -05:00
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/// <returns>GPU virtual address of the mapping</returns>
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2019-10-13 02:02:07 -04:00
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public ulong Map(ulong pa, ulong va, ulong size)
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{
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lock (_pageTable)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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return va;
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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2020-01-01 10:39:09 -05:00
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/// Maps a given range of pages to an allocated GPU virtual address.
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2019-12-30 22:22:58 -05:00
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/// The memory is automatically allocated by the memory manager.
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/// </summary>
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/// <param name="pa">CPU virtual address to map into</param>
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2020-01-01 18:14:18 -05:00
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/// <param name="size">Size in bytes of the mapping</param>
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2019-12-30 22:22:58 -05:00
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/// <returns>GPU virtual address where the range was mapped, or an all ones mask in case of failure</returns>
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2019-10-13 02:02:07 -04:00
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public ulong Map(ulong pa, ulong size)
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{
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lock (_pageTable)
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{
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ulong va = GetFreePosition(size);
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if (va != PteUnmapped)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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return va;
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}
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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2020-01-01 10:39:09 -05:00
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/// Maps a given range of pages to an allocated GPU virtual address.
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2019-12-30 22:22:58 -05:00
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/// The memory is automatically allocated by the memory manager.
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/// This also ensures that the mapping is always done in the first 4GB of GPU address space.
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/// </summary>
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/// <param name="pa">CPU virtual address to map into</param>
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2020-01-01 18:14:18 -05:00
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/// <param name="size">Size in bytes of the mapping</param>
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2019-12-30 22:22:58 -05:00
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/// <returns>GPU virtual address where the range was mapped, or an all ones mask in case of failure</returns>
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2019-10-13 02:02:07 -04:00
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public ulong MapLow(ulong pa, ulong size)
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{
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lock (_pageTable)
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{
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ulong va = GetFreePosition(size, 1, PageSize);
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if (va != PteUnmapped && va <= uint.MaxValue && (va + size) <= uint.MaxValue)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, pa + offset);
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}
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}
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else
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{
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va = PteUnmapped;
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}
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return va;
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}
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Reserves memory at a fixed GPU memory location.
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/// This prevents the reserved region from being used for memory allocation for map.
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/// </summary>
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2019-12-30 23:46:57 -05:00
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/// <param name="va">GPU virtual address to reserve</param>
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2020-01-01 18:14:18 -05:00
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/// <param name="size">Size in bytes of the reservation</param>
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2019-12-30 22:22:58 -05:00
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/// <returns>GPU virtual address of the reservation, or an all ones mask in case of failure</returns>
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2019-10-13 02:02:07 -04:00
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public ulong ReserveFixed(ulong va, ulong size)
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{
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lock (_pageTable)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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if (IsPageInUse(va + offset))
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{
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return PteUnmapped;
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}
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}
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PteReserved);
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}
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}
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return va;
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Reserves memory at any GPU memory location.
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/// </summary>
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2020-01-01 18:14:18 -05:00
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/// <param name="size">Size in bytes of the reservation</param>
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2019-12-30 22:22:58 -05:00
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/// <param name="alignment">Reservation address alignment in bytes</param>
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/// <returns>GPU virtual address of the reservation, or an all ones mask in case of failure</returns>
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2019-10-13 02:02:07 -04:00
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public ulong Reserve(ulong size, ulong alignment)
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{
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lock (_pageTable)
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{
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ulong address = GetFreePosition(size, alignment);
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if (address != PteUnmapped)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(address + offset, PteReserved);
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}
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}
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return address;
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}
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Frees memory that was previously allocated by a map or reserved.
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/// </summary>
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/// <param name="va">GPU virtual address to free</param>
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/// <param name="size">Size in bytes of the region being freed</param>
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2019-10-13 02:02:07 -04:00
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public void Free(ulong va, ulong size)
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{
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lock (_pageTable)
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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SetPte(va + offset, PteUnmapped);
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}
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}
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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2020-01-01 18:14:18 -05:00
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/// Gets the address of an unused (free) region of the specified size.
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2019-12-30 22:22:58 -05:00
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/// </summary>
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/// <param name="size">Size of the region in bytes</param>
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/// <param name="alignment">Required alignment of the region address in bytes</param>
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/// <param name="start">Start address of the search on the address space</param>
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/// <returns>GPU virtual address of the allocation, or an all ones mask in case of failure</returns>
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2019-10-13 02:02:07 -04:00
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private ulong GetFreePosition(ulong size, ulong alignment = 1, ulong start = 1UL << 32)
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{
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// Note: Address 0 is not considered valid by the driver,
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// when 0 is returned it's considered a mapping error.
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ulong address = start;
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ulong freeSize = 0;
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if (alignment == 0)
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{
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alignment = 1;
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}
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alignment = (alignment + PageMask) & ~PageMask;
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while (address + freeSize < AddressSpaceSize)
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{
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if (!IsPageInUse(address + freeSize))
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{
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freeSize += PageSize;
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if (freeSize >= size)
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{
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return address;
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}
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}
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else
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{
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address += freeSize + PageSize;
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freeSize = 0;
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ulong remainder = address % alignment;
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if (remainder != 0)
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{
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address = (address - remainder) + alignment;
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}
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}
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}
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return PteUnmapped;
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Gets the number of mapped or reserved pages on a given region.
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/// </summary>
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/// <param name="gpuVa">Start GPU virtual address of the region</param>
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/// <returns>Mapped size in bytes of the specified region</returns>
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2019-10-13 02:02:07 -04:00
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internal ulong GetSubSize(ulong gpuVa)
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{
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ulong size = 0;
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while (GetPte(gpuVa + size) != PteUnmapped)
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{
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size += PageSize;
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}
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return size;
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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2020-01-01 18:14:18 -05:00
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/// Translates a GPU virtual address to a CPU virtual address.
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2019-12-30 22:22:58 -05:00
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/// </summary>
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/// <param name="gpuVa">GPU virtual address to be translated</param>
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/// <returns>CPU virtual address</returns>
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2019-12-31 19:08:02 -05:00
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public ulong Translate(ulong gpuVa)
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{
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ulong baseAddress = GetPte(gpuVa);
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if (baseAddress == PteUnmapped || baseAddress == PteReserved)
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{
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return PteUnmapped;
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}
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return baseAddress + (gpuVa & PageMask);
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Checks if a given memory region is currently unmapped.
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/// </summary>
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/// <param name="gpuVa">Start GPU virtual address of the region</param>
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/// <param name="size">Size in bytes of the region</param>
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/// <returns>True if the region is unmapped (free), false otherwise</returns>
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public bool IsRegionFree(ulong gpuVa, ulong size)
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2019-10-13 02:02:07 -04:00
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{
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for (ulong offset = 0; offset < size; offset += PageSize)
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{
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2019-12-30 22:22:58 -05:00
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if (IsPageInUse(gpuVa + offset))
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2019-10-13 02:02:07 -04:00
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{
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return false;
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}
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}
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return true;
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Checks if a given memory page is mapped or reserved.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address of the page</param>
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/// <returns>True if the page is mapped or reserved, false otherwise</returns>
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private bool IsPageInUse(ulong gpuVa)
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2019-10-13 02:02:07 -04:00
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{
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2019-12-30 22:22:58 -05:00
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if (gpuVa >> PtLvl0Bits + PtLvl1Bits + PtPageBits != 0)
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2019-10-13 02:02:07 -04:00
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{
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return false;
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}
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2019-12-30 22:22:58 -05:00
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ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask;
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2019-10-13 02:02:07 -04:00
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if (_pageTable[l0] == null)
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{
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return false;
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}
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return _pageTable[l0][l1] != PteUnmapped;
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Gets the Page Table entry for a given GPU virtual address.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address</param>
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/// <returns>Page table entry (CPU virtual address)</returns>
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private ulong GetPte(ulong gpuVa)
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2019-10-13 02:02:07 -04:00
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{
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2019-12-30 22:22:58 -05:00
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ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask;
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2019-10-13 02:02:07 -04:00
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if (_pageTable[l0] == null)
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{
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return PteUnmapped;
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}
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return _pageTable[l0][l1];
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}
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2019-12-30 22:22:58 -05:00
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/// <summary>
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/// Sets a Page Table entry at a given GPU virtual address.
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/// </summary>
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/// <param name="gpuVa">GPU virtual address</param>
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/// <param name="pte">Page table entry (CPU virtual address)</param>
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private void SetPte(ulong gpuVa, ulong pte)
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2019-10-13 02:02:07 -04:00
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{
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2019-12-30 22:22:58 -05:00
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ulong l0 = (gpuVa >> PtLvl0Bit) & PtLvl0Mask;
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ulong l1 = (gpuVa >> PtLvl1Bit) & PtLvl1Mask;
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2019-10-13 02:02:07 -04:00
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if (_pageTable[l0] == null)
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{
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_pageTable[l0] = new ulong[PtLvl1Size];
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for (ulong index = 0; index < PtLvl1Size; index++)
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{
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_pageTable[l0][index] = PteUnmapped;
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|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-12-30 22:22:58 -05:00
|
|
|
_pageTable[l0][l1] = pte;
|
2019-10-13 02:02:07 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|