ryujinx/Ryujinx/Cpu/Decoder/AOpCodeSimdReg.cs

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2018-02-04 18:08:20 -05:00
using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdReg : AOpCodeSimd
{
public int Rm { get; private set; }
public bool Bit3 { get; private set; }
public AOpCodeSimdReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rm = (OpCode >> 16) & 0x1f;
Bit3 = ((OpCode >> 3) & 0x1) != 0;
}
}
}