Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
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using ARMeilleure.Common;
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namespace ARMeilleure.Decoders
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{
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static class DecoderHelper
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{
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2019-12-07 07:45:32 -05:00
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static DecoderHelper()
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{
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Imm8ToFP32Table = BuildImm8ToFP32Table();
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Imm8ToFP64Table = BuildImm8ToFP64Table();
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}
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public static readonly uint[] Imm8ToFP32Table;
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public static readonly ulong[] Imm8ToFP64Table;
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private static uint[] BuildImm8ToFP32Table()
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{
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uint[] tbl = new uint[256];
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for (int idx = 0; idx < 256; idx++)
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{
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tbl[idx] = ExpandImm8ToFP32((uint)idx);
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}
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return tbl;
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}
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private static ulong[] BuildImm8ToFP64Table()
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{
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ulong[] tbl = new ulong[256];
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for (int idx = 0; idx < 256; idx++)
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{
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tbl[idx] = ExpandImm8ToFP64((ulong)idx);
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}
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return tbl;
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}
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// abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b)
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private static uint ExpandImm8ToFP32(uint imm)
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{
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uint MoveBit(uint bits, int from, int to)
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{
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return ((bits >> from) & 1U) << to;
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}
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return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) |
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MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) |
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MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) |
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MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) |
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MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) |
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MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) |
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MoveBit(imm, 0, 19);
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}
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// abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b)
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private static ulong ExpandImm8ToFP64(ulong imm)
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{
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ulong MoveBit(ulong bits, int from, int to)
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{
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return ((bits >> from) & 1UL) << to;
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}
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return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) |
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MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) |
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MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) |
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MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) |
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MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) |
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MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) |
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MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) |
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MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48);
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}
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 14:56:22 -04:00
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public struct BitMask
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{
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public long WMask;
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public long TMask;
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public int Pos;
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public int Shift;
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public bool IsUndefined;
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public static BitMask Invalid => new BitMask { IsUndefined = true };
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}
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public static BitMask DecodeBitMask(int opCode, bool immediate)
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{
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int immS = (opCode >> 10) & 0x3f;
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int immR = (opCode >> 16) & 0x3f;
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int n = (opCode >> 22) & 1;
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int sf = (opCode >> 31) & 1;
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int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6));
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if (length < 1 || (sf == 0 && n != 0))
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{
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return BitMask.Invalid;
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}
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int size = 1 << length;
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int levels = size - 1;
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int s = immS & levels;
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int r = immR & levels;
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if (immediate && s == levels)
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{
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return BitMask.Invalid;
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}
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long wMask = BitUtils.FillWithOnes(s + 1);
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long tMask = BitUtils.FillWithOnes(((s - r) & levels) + 1);
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if (r > 0)
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{
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wMask = BitUtils.RotateRight(wMask, r, size);
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wMask &= BitUtils.FillWithOnes(size);
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}
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return new BitMask()
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{
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WMask = BitUtils.Replicate(wMask, size),
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TMask = BitUtils.Replicate(tMask, size),
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Pos = immS,
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Shift = immR
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};
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}
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public static long DecodeImm24_2(int opCode)
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{
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return ((long)opCode << 40) >> 38;
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}
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public static long DecodeImm26_2(int opCode)
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{
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return ((long)opCode << 38) >> 36;
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}
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public static long DecodeImmS19_2(int opCode)
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{
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return (((long)opCode << 40) >> 43) & ~3;
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}
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public static long DecodeImmS14_2(int opCode)
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{
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return (((long)opCode << 45) >> 48) & ~3;
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}
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}
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}
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