2018-03-13 23:12:05 -04:00
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using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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using System;
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2018-03-13 23:12:05 -04:00
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using System.Reflection.Emit;
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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using System.Runtime.Intrinsics.X86;
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2018-03-13 23:12:05 -04:00
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Crc32b(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32b));
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}
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public static void Crc32h(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32h));
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}
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public static void Crc32w(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32w));
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}
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public static void Crc32x(AILEmitterCtx Context)
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32x));
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}
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public static void Crc32cb(AILEmitterCtx Context)
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{
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(uint), typeof(byte));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cb));
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}
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2018-03-13 23:12:05 -04:00
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}
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public static void Crc32ch(AILEmitterCtx Context)
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{
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(uint), typeof(ushort));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32ch));
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}
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2018-03-13 23:12:05 -04:00
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}
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public static void Crc32cw(AILEmitterCtx Context)
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{
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(uint), typeof(uint));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cw));
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}
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2018-03-13 23:12:05 -04:00
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}
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public static void Crc32cx(AILEmitterCtx Context)
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{
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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if (AOptimizations.UseSse42)
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{
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EmitSse42Crc32(Context, typeof(ulong), typeof(ulong));
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}
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else
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{
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EmitCrc32(Context, nameof(ASoftFallback.Crc32cx));
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}
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}
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private static void EmitSse42Crc32(AILEmitterCtx Context, Type TCrc, Type TData)
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{
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AOpCodeAluRs Op = (AOpCodeAluRs)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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Context.EmitLdintzr(Op.Rm);
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Context.EmitCall(typeof(Sse42).GetMethod(nameof(Sse42.Crc32), new Type[] { TCrc, TData }));
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Context.EmitStintzr(Op.Rd);
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2018-03-13 23:12:05 -04:00
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}
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private static void EmitCrc32(AILEmitterCtx Context, string Name)
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{
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AOpCodeAluRs Op = (AOpCodeAluRs)Context.CurrOp;
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Context.EmitLdintzr(Op.Rn);
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if (Op.RegisterSize != ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U4);
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}
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Context.EmitLdintzr(Op.Rm);
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ASoftFallback.EmitCall(Context, Name);
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if (Op.RegisterSize != ARegisterSize.Int32)
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{
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Context.Emit(OpCodes.Conv_U8);
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}
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Context.EmitStintzr(Op.Rd);
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}
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}
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 21:32:29 -04:00
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}
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