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Implement Zip1, Zip2 (#25)

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Merry 2018-02-20 10:41:55 +00:00 • committed by gdkchan
parent 770cb4b655
commit 1039797c30
3 changed files with 81 additions and 0 deletions
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2
Ryujinx/Cpu/AOpCodeTable.cs
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@ -256,6 +256,8 @@ namespace ChocolArm64
Set("0x001110xx0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg));
Set("0x001110xx0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg));
Set("0x001110<<100001001010xxxxxxxxxx", AInstEmit.Xtn_V, typeof(AOpCodeSimd));
Set("0x001110xx0xxxxx001110xxxxxxxxxx", AInstEmit.Zip1_V, typeof(AOpCodeSimdReg));
Set("0x001110xx0xxxxx011110xxxxxxxxxx", AInstEmit.Zip2_V, typeof(AOpCodeSimdReg));
#endregion
}

34
Ryujinx/Cpu/Instruction/AInstEmitSimdMove.cs
View file

@ -263,6 +263,16 @@ namespace ChocolArm64.Instruction
}
}
public static void Zip1_V(AILEmitterCtx Context)
{
EmitVectorZip(Context, Part: 0);
}
public static void Zip2_V(AILEmitterCtx Context)
{
EmitVectorZip(Context, Part: 1);
}
private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
{
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
@ -295,5 +305,29 @@ namespace ChocolArm64.Instruction
EmitVectorZeroUpper(Context, Op.Rd);
}
}
private static void EmitVectorZip(AILEmitterCtx Context, int Part)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Elems = Bytes >> Op.Size;
int Half = Elems >> 1;
for (int Index = 0; Index < Elems; Index++)
{
int Elem = Part * Half + (Index >> 1);
EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size);
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
}
}