CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements

Ryujinx/Cpu/Decoder/AOpCodeSimdMemMs.cs

@@ -37,6 +37,8 @@ namespace ChocolArm64.Decoder
                 return;
             }
 
+            Extend64 = false;
+
             RegisterSize = Q
                 ? ARegisterSize.SIMD128
                 : ARegisterSize.SIMD64;