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Fix for some SIMD issues

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This commit is contained in:
gdkchan 2018-02-18 01:57:33 -03:00
parent f469b968a8
commit 1c44d9f66d
13 changed files with 124 additions and 36 deletions
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10
Ryujinx/Cpu/Instruction/AInstEmitSimdCvt.cs
View file

@ -246,6 +246,11 @@ namespace ChocolArm64.Instruction
EmitScalarFcvtu(Context, Op.Size, Op.FBits);
}
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
{
Context.Emit(OpCodes.Conv_U8);
}
Context.EmitStintzr(Op.Rd);
}
@ -314,6 +319,11 @@ namespace ChocolArm64.Instruction
: nameof(ASoftFallback.SatF64ToU64));
}
if (SizeF == 0)
{
Context.Emit(OpCodes.Conv_U8);
}
EmitVectorInsert(Context, Op.Rd, Index, SizeI);
}

63
Ryujinx/Cpu/Instruction/AInstEmitSimdHelper.cs
View file

@ -210,17 +210,17 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
EmitVectorOpF(Context, Emit, OperFlags.RnRm, Op.Index);
EmitVectorOpByElemF(Context, Emit, Op.Index);
}
public static void EmitVectorTernaryOpByElemF(AILEmitterCtx Context, Action Emit)
{
AOpCodeSimdRegElem Op = (AOpCodeSimdRegElem)Context.CurrOp;
EmitVectorOpF(Context, Emit, OperFlags.RdRnRm, Op.Index);
EmitVectorOpByElemF(Context, Emit, Op.Index);
}
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers, int Elem = -1)
public static void EmitVectorOpF(AILEmitterCtx Context, Action Emit, OperFlags Opers)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@ -242,14 +242,7 @@ namespace ChocolArm64.Instruction
if (Opers.HasFlag(OperFlags.Rm))
{
if (Elem != -1)
{
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
}
else
{
EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
}
EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
}
Emit();
@ -263,6 +256,33 @@ namespace ChocolArm64.Instruction
}
}
public static void EmitVectorOpByElemF(AILEmitterCtx Context, Action Emit, int Elem)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int SizeF = Op.Size & 1;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
for (int Index = 0; Index < (Bytes >> SizeF + 2); Index++)
{
EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
Emit();
EmitVectorInsertTmpF(Context, Index, SizeF);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void EmitVectorUnaryOpSx(AILEmitterCtx Context, Action Emit)
{
EmitVectorOp(Context, Emit, OperFlags.Rn, true);
@ -534,5 +554,26 @@ namespace ChocolArm64.Instruction
Context.EmitStvec(Reg);
}
public static void EmitVectorInsertTmpF(AILEmitterCtx Context, int Index, int Size)
{
Context.EmitLdvectmp();
Context.EmitLdc_I4(Index);
if (Size == 0)
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertSingle));
}
else if (Size == 1)
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.VectorInsertDouble));
}
else
{
throw new ArgumentOutOfRangeException(nameof(Size));
}
Context.EmitStvectmp();
}
}
}

26
Ryujinx/Cpu/Instruction/AInstEmitSimdMove.cs
View file

@ -85,6 +85,8 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rn, 0, 3);
EmitIntZeroHigherIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
@ -94,6 +96,8 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rn, 1, 3);
EmitIntZeroHigherIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
@ -103,6 +107,8 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
EmitIntZeroHigherIfNeeded(Context);
EmitScalarSet(Context, Op.Rd, 3);
}
@ -112,6 +118,8 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
EmitIntZeroHigherIfNeeded(Context);
EmitVectorInsert(Context, Op.Rd, 1, 3);
}
@ -137,12 +145,19 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
for (int Index = 0; Index < (4 >> Op.Size); Index++)
int Elems = Op.RegisterSize == ARegisterSize.SIMD128 ? 4 : 2;
for (int Index = 0; Index < (Elems >> Op.Size); Index++)
{
Context.EmitLdc_I8(Op.Imm);
EmitVectorInsert(Context, Op.Rd, Index, Op.Size + 2);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Ins_Gp(AILEmitterCtx Context)
@ -248,6 +263,15 @@ namespace ChocolArm64.Instruction
}
}
private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
{
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
{
Context.Emit(OpCodes.Conv_U4);
Context.Emit(OpCodes.Conv_U8);
}
}
private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;