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Fix for some SIMD issues

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This commit is contained in:
gdkchan 2018-02-18 01:57:33 -03:00
parent f469b968a8
commit 1c44d9f66d
13 changed files with 124 additions and 36 deletions
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26
Ryujinx/Cpu/Instruction/AInstEmitSimdMove.cs
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@ -85,6 +85,8 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rn, 0, 3);
EmitIntZeroHigherIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
@ -94,6 +96,8 @@ namespace ChocolArm64.Instruction
EmitVectorExtractZx(Context, Op.Rn, 1, 3);
EmitIntZeroHigherIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
@ -103,6 +107,8 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
EmitIntZeroHigherIfNeeded(Context);
EmitScalarSet(Context, Op.Rd, 3);
}
@ -112,6 +118,8 @@ namespace ChocolArm64.Instruction
Context.EmitLdintzr(Op.Rn);
EmitIntZeroHigherIfNeeded(Context);
EmitVectorInsert(Context, Op.Rd, 1, 3);
}
@ -137,12 +145,19 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdImm Op = (AOpCodeSimdImm)Context.CurrOp;
for (int Index = 0; Index < (4 >> Op.Size); Index++)
int Elems = Op.RegisterSize == ARegisterSize.SIMD128 ? 4 : 2;
for (int Index = 0; Index < (Elems >> Op.Size); Index++)
{
Context.EmitLdc_I8(Op.Imm);
EmitVectorInsert(Context, Op.Rd, Index, Op.Size + 2);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Ins_Gp(AILEmitterCtx Context)
@ -248,6 +263,15 @@ namespace ChocolArm64.Instruction
}
}
private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context)
{
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
{
Context.Emit(OpCodes.Conv_U4);
Context.Emit(OpCodes.Conv_U8);
}
}
private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;