Fix for some SIMD issues

Ryujinx/Cpu/Translation/AILBlock.cs

@@ -26,7 +26,7 @@ namespace ChocolArm64.Translation
         {
             if (ILEmitter is AILOpCodeLoad Ld && AILEmitter.IsRegIndex(Ld.Index))
             {
-                switch (Ld.IoType & AIoType.Mask)
+                switch (Ld.IoType)
                 {
                     case AIoType.Flag:   IntInputs |= ((1L << Ld.Index) << 32) & ~IntOutputs; break;
                     case AIoType.Int:    IntInputs |=  (1L << Ld.Index)        & ~IntOutputs; break;
@@ -37,7 +37,7 @@ namespace ChocolArm64.Translation
             {
                 if (AILEmitter.IsRegIndex(St.Index))
                 {
-                    switch (St.IoType & AIoType.Mask)
+                    switch (St.IoType)
                     {
                         case AIoType.Flag:   IntOutputs |= (1L << St.Index) << 32; break;
                         case AIoType.Int:    IntOutputs |=  1L << St.Index;        break;

Ryujinx/Cpu/Translation/AILOpCodeLoad.cs

@@ -22,7 +22,7 @@ namespace ChocolArm64.Translation
 
         public void Emit(AILEmitter Context)
         {
-            switch (IoType & AIoType.Mask)
+            switch (IoType)
             {
                 case AIoType.Arg: Context.Generator.EmitLdarg(Index); break;
 

Ryujinx/Cpu/Translation/AILOpCodeStore.cs

@@ -22,7 +22,7 @@ namespace ChocolArm64.Translation
 
         public void Emit(AILEmitter Context)
         {
-            switch (IoType & AIoType.Mask)
+            switch (IoType)
             {
                 case AIoType.Arg: Context.Generator.EmitStarg(Index); break;
 

Ryujinx/Cpu/Translation/AIoType.cs

@@ -10,9 +10,6 @@ namespace ChocolArm64.Translation
         Flag,
         Int,
         Float,
-        Vector,
-        Mask    = 0xff,
-        VectorI = Vector | 1 << 8,
-        VectorF = Vector | 1 << 9
+        Vector
     }
 }