Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
* Update SoftFloat.cs * Update SoftFallback.cs * Update InstEmitSimdShift.cs * Update InstEmitSimdCvt.cs * Update InstEmitSimdArithmetic.cs * Update CryptoHelper.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuThreadState.cs * Update OpCodeTable.cs * Add files via upload * Nit. * Remove unused using. Nit. * Remove unused using. FZ update. * Nit. * Remove unused using.
This commit is contained in:
LDj3SNuD
gdkchan
parent
53e6664526
commit
1e7ea76f14
28 changed files with 5843 additions and 5639 deletions
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@ -1,12 +1,10 @@
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#define AluImm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("AluImm")] // Tested: second half of 2018.
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[Category("AluImm")]
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public sealed class CpuTestAluImm : CpuTest
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{
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#if AluImm
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@ -16,436 +14,420 @@ namespace Ryujinx.Tests.Cpu
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private const int RndCntImmr = 2;
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[Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
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public void Add_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Add_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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uint opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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CpuThreadState ThreadState;
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if (Rn != 31)
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if (rn != 31)
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{
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ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
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SingleOpcode(opcode, x1: xnSp);
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}
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else
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{
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ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
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SingleOpcode(opcode, x31: xnSp);
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}
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
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public void Add_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Add_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint Opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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uint opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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CpuThreadState ThreadState;
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if (Rn != 31)
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if (rn != 31)
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{
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ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
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SingleOpcode(opcode, x1: wnWsp);
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}
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else
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{
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ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
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SingleOpcode(opcode, x31: wnWsp);
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}
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
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public void Adds_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Adds_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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uint opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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CpuThreadState ThreadState;
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if (Rn != 31)
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if (rn != 31)
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{
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ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
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SingleOpcode(opcode, x1: xnSp);
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}
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else
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{
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ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
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SingleOpcode(opcode, x31: xnSp);
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}
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
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public void Adds_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Adds_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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{
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uint Opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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uint opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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CpuThreadState ThreadState;
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if (Rn != 31)
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if (rn != 31)
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{
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ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
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SingleOpcode(opcode, x1: wnWsp);
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}
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else
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{
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ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
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SingleOpcode(opcode, x31: wnWsp);
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}
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
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public void And_N1_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void And_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0x92400000; // AND X0, X0, #0x1
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0x92400000; // AND X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
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public void And_N0_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void And_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0x92000000; // AND X0, X0, #0x100000001
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0x92000000; // AND X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("AND <Wd|WSP>, <Wn>, #<imm>")]
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public void And_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void And_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0x12000000; // AND W0, W0, #0x1
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0x12000000; // AND W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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SingleOpcode(opcode, x1: wn, x31: w31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
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public void Ands_N1_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Ands_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0xF2400000; // ANDS X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
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public void Ands_N0_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Ands_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ANDS <Wd>, <Wn>, #<imm>")]
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public void Ands_32bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Ands_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0x72000000; // ANDS W0, W0, #0x1
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0x72000000; // ANDS W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint _W31 = TestContext.CurrentContext.Random.NextUInt();
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
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SingleOpcode(opcode, x1: wn, x31: w31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
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public void Eor_N1_64bit([Values(0u, 31u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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public void Eor_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
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{
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uint Opcode = 0xD2400000; // EOR X0, X0, #0x1
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint opcode = 0xD2400000; // EOR X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong _X31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
|
||||
SingleOpcode(opcode, x1: xn, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
|
||||
public void Eor_N0_64bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Eor_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
{
|
||||
uint Opcode = 0xD2000000; // EOR X0, X0, #0x100000001
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
uint opcode = 0xD2000000; // EOR X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
|
||||
SingleOpcode(opcode, x1: xn, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("EOR <Wd>, <Wn>, #<imm>")]
|
||||
public void Eor_32bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Eor_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
{
|
||||
uint Opcode = 0x52000000; // EOR W0, W0, #0x1
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
uint opcode = 0x52000000; // EOR W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
|
||||
SingleOpcode(opcode, x1: wn, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
|
||||
public void Orr_N1_64bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Orr_N1_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
|
||||
{
|
||||
uint Opcode = 0xB2400000; // ORR X0, X0, #0x1
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
uint opcode = 0xB2400000; // ORR X0, X0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
|
||||
SingleOpcode(opcode, x1: xn, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
|
||||
public void Orr_N0_64bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Orr_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
{
|
||||
uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
uint opcode = 0xB2000000; // ORR X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
|
||||
CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
|
||||
SingleOpcode(opcode, x1: xn, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Wd|WSP>, <Wn>, #<imm>")]
|
||||
public void Orr_32bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Orr_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
|
||||
{
|
||||
uint Opcode = 0x32000000; // ORR W0, W0, #0x1
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
uint opcode = 0x32000000; // ORR W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
CpuThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
|
||||
SingleOpcode(opcode, x1: wn, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
public void Sub_64bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Sub_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint Opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
uint opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
|
||||
CpuThreadState ThreadState;
|
||||
|
||||
if (Rn != 31)
|
||||
if (rn != 31)
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
|
||||
SingleOpcode(opcode, x1: xnSp);
|
||||
}
|
||||
else
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
|
||||
SingleOpcode(opcode, x31: xnSp);
|
||||
}
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
|
||||
public void Sub_32bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Sub_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
uint opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
|
||||
CpuThreadState ThreadState;
|
||||
|
||||
if (Rn != 31)
|
||||
if (rn != 31)
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
|
||||
SingleOpcode(opcode, x1: wnWsp);
|
||||
}
|
||||
else
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
|
||||
SingleOpcode(opcode, x31: wnWsp);
|
||||
}
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
public void Subs_64bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Subs_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xnSp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint Opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
uint opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
|
||||
CpuThreadState ThreadState;
|
||||
|
||||
if (Rn != 31)
|
||||
if (rn != 31)
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
|
||||
SingleOpcode(opcode, x1: xnSp);
|
||||
}
|
||||
else
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
|
||||
SingleOpcode(opcode, x31: xnSp);
|
||||
}
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
|
||||
public void Subs_32bit([Values(0u, 31u)] uint Rd,
|
||||
[Values(1u, 31u)] uint Rn,
|
||||
public void Subs_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
|
||||
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wnWsp,
|
||||
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
{
|
||||
uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
uint opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
|
||||
|
||||
CpuThreadState ThreadState;
|
||||
|
||||
if (Rn != 31)
|
||||
if (rn != 31)
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
|
||||
SingleOpcode(opcode, x1: wnWsp);
|
||||
}
|
||||
else
|
||||
{
|
||||
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
|
||||
SingleOpcode(opcode, x31: wnWsp);
|
||||
}
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue