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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)

Browse source 
* Update SoftFloat.cs

* Update SoftFallback.cs

* Update InstEmitSimdShift.cs

* Update InstEmitSimdCvt.cs

* Update InstEmitSimdArithmetic.cs

* Update CryptoHelper.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuThreadState.cs

* Update OpCodeTable.cs

* Add files via upload

* Nit.

* Remove unused using. Nit.

* Remove unused using. FZ update.

* Nit.

* Remove unused using.
This commit is contained in:
LDj3SNuD 2018-11-01 05:22:09 +01:00 • committed by gdkchan
parent 53e6664526
commit 1e7ea76f14
28 changed files with 5843 additions and 5639 deletions
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80
Ryujinx.Tests/Cpu/CpuTestMov.cs
View file

@ -1,111 +1,109 @@
#define Mov
using ChocolArm64.State;
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
[Category("Mov")] // Tested: second half of 2018.
[Category("Mov")]
public sealed class CpuTestMov : CpuTest
{
#if Mov
private const int RndCntImm = 2;
[Test, Pairwise, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
public void Movk_64bit([Values(0u, 31u)] uint Rd,
[Random(RndCntImm)] ulong _Xd,
public void Movk_64bit([Values(0u, 31u)] uint rd,
[Random(RndCntImm)] ulong xd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint opcode = 0xF2800000; // MOVK X0, #0, LSL #0
opcode |= ((rd & 31) << 0);
opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
ulong x31 = TestContext.CurrentContext.Random.NextULong();
CpuThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31);
SingleOpcode(opcode, x0: xd, x31: x31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
public void Movk_32bit([Values(0u, 31u)] uint Rd,
[Random(RndCntImm)] uint _Wd,
public void Movk_32bit([Values(0u, 31u)] uint rd,
[Random(RndCntImm)] uint wd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint opcode = 0x72800000; // MOVK W0, #0, LSL #0
opcode |= ((rd & 31) << 0);
opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
uint w31 = TestContext.CurrentContext.Random.NextUInt();
CpuThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31);
SingleOpcode(opcode, x0: wd, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
public void Movn_64bit([Values(0u, 31u)] uint Rd,
public void Movn_64bit([Values(0u, 31u)] uint rd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint opcode = 0x92800000; // MOVN X0, #0, LSL #0
opcode |= ((rd & 31) << 0);
opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
ulong x31 = TestContext.CurrentContext.Random.NextULong();
CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
SingleOpcode(opcode, x31: x31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
public void Movn_32bit([Values(0u, 31u)] uint Rd,
public void Movn_32bit([Values(0u, 31u)] uint rd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint opcode = 0x12800000; // MOVN W0, #0, LSL #0
opcode |= ((rd & 31) << 0);
opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
uint w31 = TestContext.CurrentContext.Random.NextUInt();
CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
SingleOpcode(opcode, x31: w31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
public void Movz_64bit([Values(0u, 31u)] uint Rd,
public void Movz_64bit([Values(0u, 31u)] uint rd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
opcode |= ((rd & 31) << 0);
opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
ulong x31 = TestContext.CurrentContext.Random.NextULong();
CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
SingleOpcode(opcode, x31: x31);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
public void Movz_32bit([Values(0u, 31u)] uint Rd,
public void Movz_32bit([Values(0u, 31u)] uint rd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0
Opcode |= ((Rd & 31) << 0);
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint opcode = 0x52800000; // MOVZ W0, #0, LSL #0
opcode |= ((rd & 31) << 0);
opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
uint w31 = TestContext.CurrentContext.Random.NextUInt();
CpuThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
SingleOpcode(opcode, x31: w31);
CompareAgainstUnicorn();
}