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Reduce JIT GC allocations (#2515)

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* Turn `MemoryOperand` into a struct

* Remove `IntrinsicOperation`

* Remove `PhiNode`

* Remove `Node`

* Turn `Operand` into a struct

* Turn `Operation` into a struct

* Clean up pool management methods

* Add `Arena` allocator

* Move `OperationHelper` to `Operation.Factory`

* Move `OperandHelper` to `Operand.Factory`

* Optimize `Operation` a bit

* Fix `Arena` initialization

* Rename `NativeList<T>` to `ArenaList<T>`

* Reduce `Operand` size from 88 to 56 bytes

* Reduce `Operation` size from 56 to 40 bytes

* Add optimistic interning of Register & Constant operands

* Optimize `RegisterUsage` pass a bit

* Optimize `RemoveUnusedNodes` pass a bit

Iterating in reverse-order allows killing dependency chains in a single
pass.

* Fix PPTC symbols

* Optimize `BasicBlock` a bit

Reduce allocations from `_successor` & `DominanceFrontiers`

* Fix `Operation` resize

* Make `Arena` expandable

Change the arena allocator to be expandable by allocating in pages, with
some of them being pooled. Currently 32 pages are pooled. An LRU removal
mechanism should probably be added to it.

Apparently MHR can allocate bitmaps large enough to exceed the 16MB
limit for the type.

* Move `Arena` & `ArenaList` to `Common`

* Remove `ThreadStaticPool` & co

* Add `PhiOperation`

* Reduce `Operand` size from 56 from 48 bytes

* Add linear-probing to `Operand` intern table

* Optimize `HybridAllocator` a bit

* Add `Allocators` class

* Tune `ArenaAllocator` sizes

* Add page removal mechanism to `ArenaAllocator`

Remove pages which have not been used for more than 5s after each reset.

I am on fence if this would be better using a Gen2 callback object like
the one in System.Buffers.ArrayPool<T>, to trim the pool. Because right
now if a large translation happens, the pages will be freed only after a
reset. This reset may not happen for a while because no new translation
is hit, but the arena base sizes are rather small.

* Fix `OOM` when allocating larger than page size in `ArenaAllocator`

Tweak resizing mechanism for Operand.Uses and Assignemnts.

* Optimize `Optimizer` a bit

* Optimize `Operand.Add<T>/Remove<T>` a bit

* Clean up `PreAllocator`

* Fix phi insertion order

Reduce codegen diffs.

* Fix code alignment

* Use new heuristics for degree of parallelism

* Suppress warnings

* Address gdkchan's feedback

Renamed `GetValue()` to `GetValueUnsafe()` to make it more clear that
`Operand.Value` should usually not be modified directly.

* Add fast path to `ArenaAllocator`

* Assembly for `ArenaAllocator.Allocate(ulong)`:

  .L0:
    mov rax, [rcx+0x18]
    lea r8, [rax+rdx]
    cmp r8, [rcx+0x10]
    ja short .L2
  .L1:
    mov rdx, [rcx+8]
    add rax, [rdx+8]
    mov [rcx+0x18], r8
    ret
  .L2:
    jmp ArenaAllocator.AllocateSlow(UInt64)

  A few variable/field had to be changed to ulong so that RyuJIT avoids
  emitting zero-extends.

* Implement a new heuristic to free pooled pages.

  If an arena is used often, it is more likely that its pages will be
  needed, so the pages are kept for longer (e.g: during PPTC rebuild or
  burst sof compilations). If is not used often, then it is more likely
  that its pages will not be needed (e.g: after PPTC rebuild or bursts
  of compilations).

* Address riperiperi's feedback

* Use `EqualityComparer<T>` in `IntrusiveList<T>`

Avoids a potential GC hole in `Equals(T, T)`.
This commit is contained in:
FICTURE7 2021-08-17 22:08:34 +04:00 • committed by GitHub
parent cd4530f29c
commit 22b2cb39af
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
91 changed files with 2354 additions and 2142 deletions
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2
ARMeilleure/Instructions/InstEmitAlu.cs
View file

@ -6,7 +6,7 @@ using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitAlu32.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitAluHelper.cs
View file

@ -6,7 +6,7 @@ using System;
using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitBfm.cs
View file

@ -3,7 +3,7 @@ using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitCcmp.cs
View file

@ -6,7 +6,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitCsel.cs
View file

@ -4,7 +4,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitDiv.cs
View file

@ -3,7 +3,7 @@ using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitException.cs
View file

@ -1,7 +1,7 @@
using ARMeilleure.Decoders;
using ARMeilleure.Translation;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitException32.cs
View file

@ -2,7 +2,7 @@
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitFlow.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitFlow32.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

4
ARMeilleure/Instructions/InstEmitFlowHelper.cs
View file

@ -6,7 +6,7 @@ using ARMeilleure.Translation.Cache;
using ARMeilleure.Translation.PTC;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -28,7 +28,7 @@ namespace ARMeilleure.Instructions
{
Operand cmpResult = context.TryGetComparisonResult(condition);
if (cmpResult != null)
if (cmpResult != default)
{
return cmpResult;
}

2
ARMeilleure/Instructions/InstEmitHashHelper.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using System;
using System.Diagnostics;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
namespace ARMeilleure.Instructions

2
ARMeilleure/Instructions/InstEmitHelper.cs
View file

@ -4,7 +4,7 @@ using ARMeilleure.State;
using ARMeilleure.Translation;
using System;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

4
ARMeilleure/Instructions/InstEmitMemory.cs
View file

@ -4,7 +4,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -121,7 +121,7 @@ namespace ARMeilleure.Instructions
private static Operand GetAddress(ArmEmitterContext context, long addend = 0)
{
Operand address = null;
Operand address = default;
switch (context.CurrOp)
{

4
ARMeilleure/Instructions/InstEmitMemory32.cs
View file

@ -6,7 +6,7 @@ using System;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -156,7 +156,7 @@ namespace ARMeilleure.Instructions
Operand n = context.Copy(GetIntA32(context, op.Rn));
Operand m = GetMemM(context, setCarry: false);
Operand temp = null;
Operand temp = default;
if (op.Index || op.WBack)
{

2
ARMeilleure/Instructions/InstEmitMemoryEx.cs
View file

@ -6,7 +6,7 @@ using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitMemoryEx32.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryExHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

6
ARMeilleure/Instructions/InstEmitMemoryExHelper.cs
View file

@ -3,7 +3,7 @@ using ARMeilleure.State;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -20,7 +20,7 @@ namespace ARMeilleure.Instructions
if (size == 4)
{
// Only 128-bit CAS is guaranteed to have a atomic load.
Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, null, write: false, 4);
Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, default, write: false, 4);
Operand zero = context.VectorZero();
@ -109,7 +109,7 @@ namespace ARMeilleure.Instructions
context.BranchIfTrue(lblExit, exFailed);
// STEP 2: We have exclusive access and the address is valid, attempt the store using CAS.
Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, null, write: true, size);
Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, default, write: true, size);
Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
Operand exValue = size switch

14
ARMeilleure/Instructions/InstEmitMemoryHelper.cs
View file

@ -7,7 +7,7 @@ using System;
using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -130,7 +130,7 @@ namespace ARMeilleure.Instructions
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
Operand value = null;
Operand value = default;
switch (size)
{
@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions
throw new ArgumentOutOfRangeException(nameof(size));
}
Operand physAddr = EmitPtPointerLoad(context, address, null, write: false, size);
Operand physAddr = EmitPtPointerLoad(context, address, default, write: false, size);
return size switch
{
@ -186,7 +186,7 @@ namespace ARMeilleure.Instructions
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
Operand value = null;
Operand value = default;
switch (size)
{
@ -257,7 +257,7 @@ namespace ARMeilleure.Instructions
throw new ArgumentOutOfRangeException(nameof(size));
}
Operand physAddr = EmitPtPointerLoad(context, address, null, write: true, size);
Operand physAddr = EmitPtPointerLoad(context, address, default, write: true, size);
if (size < 3 && value.Type == OperandType.I64)
{
@ -348,7 +348,7 @@ namespace ARMeilleure.Instructions
// If the VA is out of range, or not aligned to the access size, force PTE to 0 by masking it.
pte = context.BitwiseAnd(pte, context.ShiftRightSI(context.Add(addrShifted, Const(-(long)ptLevelSize)), Const(63)));
if (lblSlowPath != null)
if (lblSlowPath != default)
{
if (write)
{
@ -505,7 +505,7 @@ namespace ARMeilleure.Instructions
case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); break;
}
Operand value = null;
Operand value = default;
if (size < 4)
{

2
ARMeilleure/Instructions/InstEmitMove.cs
View file

@ -3,7 +3,7 @@ using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitMul32.cs
View file

@ -6,7 +6,7 @@ using System;
using static ARMeilleure.Instructions.InstEmitAluHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

64
ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
View file

@ -11,7 +11,7 @@ using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -126,10 +126,10 @@ namespace ARMeilleure.Instructions
8 => Clz_V_I8 (context, GetVec(op.Rn)),
16 => Clz_V_I16(context, GetVec(op.Rn)),
32 => Clz_V_I32(context, GetVec(op.Rn)),
_ => null
_ => default
};
if (res != null)
if (res != default)
{
if (op.RegisterSize == RegisterSize.Simd64)
{
@ -159,7 +159,7 @@ namespace ARMeilleure.Instructions
{
if (!Optimizations.UseSsse3)
{
return null;
return default;
}
// CLZ nibble table.
@ -189,7 +189,7 @@ namespace ARMeilleure.Instructions
{
if (!Optimizations.UseSsse3)
{
return null;
return default;
}
Operand maskSwap = X86GetElements(context, 0x80_0f_80_0d_80_0b_80_09, 0x80_07_80_05_80_03_80_01);
@ -215,7 +215,7 @@ namespace ARMeilleure.Instructions
// TODO: Use vplzcntd when AVX-512 is supported.
if (!Optimizations.UseSse2)
{
return null;
return default;
}
Operand AddVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Paddd, op0, op1);
@ -3684,8 +3684,8 @@ namespace ARMeilleure.Instructions
Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask);
mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal));
qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : null;
sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnps, mask2, mask1) : null;
qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default;
sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnps, mask2, mask1) : default;
}
else /* if ((op.Size & 1) == 1) */
{
@ -3698,8 +3698,8 @@ namespace ARMeilleure.Instructions
Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask);
mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal));
qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : null;
sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnpd, mask2, mask1) : null;
qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default;
sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnpd, mask2, mask1) : default;
}
}
@ -3707,11 +3707,11 @@ namespace ARMeilleure.Instructions
ArmEmitterContext context,
Func2I emit,
bool scalar,
Operand n = null,
Operand m = null)
Operand n = default,
Operand m = default)
{
Operand nCopy = n ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn));
Operand mCopy = m ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm));
Operand nCopy = n == default ? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn)) : n;
Operand mCopy = m == default ? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm)) : m;
EmitSse2VectorIsNaNOpF(context, nCopy, out Operand nQNaNMask, out Operand nSNaNMask);
EmitSse2VectorIsNaNOpF(context, mCopy, out _, out Operand mSNaNMask, isQNaN: false);
@ -3734,7 +3734,7 @@ namespace ARMeilleure.Instructions
Operand res = context.AddIntrinsic(Intrinsic.X86Blendvps, resNaN, emit(nCopy, mCopy), resMask);
if (n != null || m != null)
if (n != default || m != default)
{
return res;
}
@ -3750,7 +3750,7 @@ namespace ARMeilleure.Instructions
context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rd), res);
return null;
return default;
}
else /* if (sizeF == 1) */
{
@ -3768,7 +3768,7 @@ namespace ARMeilleure.Instructions
Operand res = context.AddIntrinsic(Intrinsic.X86Blendvpd, resNaN, emit(nCopy, mCopy), resMask);
if (n != null || m != null)
if (n != default || m != default)
{
return res;
}
@ -3780,7 +3780,7 @@ namespace ARMeilleure.Instructions
context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rd), res);
return null;
return default;
}
}
@ -3788,11 +3788,11 @@ namespace ARMeilleure.Instructions
ArmEmitterContext context,
Func2I emit,
bool scalar,
Operand n = null,
Operand m = null)
Operand n = default,
Operand m = default)
{
Operand nCopy = n ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn));
Operand mCopy = m ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm));
Operand nCopy = n == default ? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn)) : n;
Operand mCopy = m == default ? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm)) : m;
EmitSseOrAvxEnterFtzAndDazModesOpF(context, out Operand isTrue);
@ -3800,7 +3800,7 @@ namespace ARMeilleure.Instructions
EmitSseOrAvxExitFtzAndDazModesOpF(context, isTrue);
if (n != null || m != null)
if (n != default || m != default)
{
return res;
}
@ -3828,7 +3828,7 @@ namespace ARMeilleure.Instructions
context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rd), res);
return null;
return default;
}
private static Operand EmitSse2VectorMaxMinOpF(ArmEmitterContext context, Operand n, Operand m, bool isMax)
@ -3865,11 +3865,11 @@ namespace ARMeilleure.Instructions
ArmEmitterContext context,
bool isMaxNum,
bool scalar,
Operand n = null,
Operand m = null)
Operand n = default,
Operand m = default)
{
Operand nCopy = n ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn));
Operand mCopy = m ?? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm));
Operand nCopy = n == default ? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rn)) : n;
Operand mCopy = m == default ? context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rm)) : m;
EmitSse2VectorIsNaNOpF(context, nCopy, out Operand nQNaNMask, out _, isQNaN: true);
EmitSse2VectorIsNaNOpF(context, mCopy, out Operand mQNaNMask, out _, isQNaN: true);
@ -3896,7 +3896,7 @@ namespace ARMeilleure.Instructions
}, scalar: scalar, op1, op2);
}, scalar: scalar, nCopy, mCopy);
if (n != null || m != null)
if (n != default || m != default)
{
return res;
}
@ -3912,7 +3912,7 @@ namespace ARMeilleure.Instructions
context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rd), res);
return null;
return default;
}
else /* if (sizeF == 1) */
{
@ -3934,7 +3934,7 @@ namespace ARMeilleure.Instructions
}, scalar: scalar, op1, op2);
}, scalar: scalar, nCopy, mCopy);
if (n != null || m != null)
if (n != default || m != default)
{
return res;
}
@ -3946,7 +3946,7 @@ namespace ARMeilleure.Instructions
context.Copy(GetVec(((OpCodeSimdReg)context.CurrOp).Rd), res);
return null;
return default;
}
}

5
ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
View file

@ -8,7 +8,7 @@ using static ARMeilleure.Instructions.InstEmitFlowHelper;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -1275,7 +1275,8 @@ namespace ARMeilleure.Instructions
{
OpCode32SimdSel op = (OpCode32SimdSel)context.CurrOp;
Operand condition = null;
Operand condition = default;
switch (op.Cc)
{
case OpCode32SimdSelMode.Eq:

2
ARMeilleure/Instructions/InstEmitSimdCmp.cs
View file

@ -6,7 +6,7 @@ using System;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSimdCmp32.cs
View file

@ -8,7 +8,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSimdCvt.cs
View file

@ -8,7 +8,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

14
ARMeilleure/Instructions/InstEmitSimdCvt32.cs
View file

@ -9,7 +9,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -391,7 +391,8 @@ namespace ARMeilleure.Instructions
Operand zero = context.VectorZero();
Operand nCmp;
Operand nIntOrLong2 = null;
Operand nIntOrLong2 = default;
if (!signed)
{
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
@ -441,7 +442,8 @@ namespace ARMeilleure.Instructions
Operand zero = context.VectorZero();
Operand nCmp;
Operand nIntOrLong2 = null;
Operand nIntOrLong2 = default;
if (!signed)
{
nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual));
@ -510,7 +512,8 @@ namespace ARMeilleure.Instructions
Operand fpMaxValMask = X86GetAllElements(context, 0x4F000000); // 2.14748365E9f (2147483648)
Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes);
Operand nInt2 = null;
Operand nInt2 = default;
if (!signed)
{
nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask);
@ -551,7 +554,8 @@ namespace ARMeilleure.Instructions
Operand fpMaxValMask = X86GetAllElements(context, 0x43E0000000000000L); // 9.2233720368547760E18d (9223372036854775808)
Operand nLong = InstEmit.EmitSse2CvtDoubleToInt64OpF(context, nRes, false);
Operand nLong2 = null;
Operand nLong2 = default;
if (!signed)
{
nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask);

12
ARMeilleure/Instructions/InstEmitSimdHelper.cs
View file

@ -7,7 +7,7 @@ using System.Diagnostics;
using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -1279,9 +1279,11 @@ namespace ARMeilleure.Instructions
context.MarkLabel(lblTrue);
}
public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = null)
public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = default)
{
isTrue ??= context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)));
isTrue = isTrue == default
? context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)))
: isTrue;
Operand lblTrue = Label();
context.BranchIfFalse(lblTrue, isTrue);
@ -1455,7 +1457,7 @@ namespace ARMeilleure.Instructions
}
else
{
Operand me = null;
Operand me = default;
if (byElem)
{
@ -1625,7 +1627,7 @@ namespace ARMeilleure.Instructions
{
ThrowIfInvalid(index, size);
Operand res = null;
Operand res = default;
switch (size)
{

4
ARMeilleure/Instructions/InstEmitSimdHelper32.cs
View file

@ -7,7 +7,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -1127,7 +1127,7 @@ namespace ARMeilleure.Instructions
{
ThrowIfInvalid(index, size);
Operand res = null;
Operand res = default;
switch (size)
{

2
ARMeilleure/Instructions/InstEmitSimdLogical.cs
View file

@ -6,7 +6,7 @@ using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSimdLogical32.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSimdMemory.cs
View file

@ -6,7 +6,7 @@ using System.Diagnostics;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSimdMemory32.cs
View file

@ -5,7 +5,7 @@ using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitMemoryHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

6
ARMeilleure/Instructions/InstEmitSimdMove.cs
View file

@ -6,7 +6,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -639,7 +639,7 @@ namespace ARMeilleure.Instructions
if (Optimizations.UseSsse3)
{
Operand mask = null;
Operand mask = default;
if (op.Size < 3)
{
@ -707,7 +707,7 @@ namespace ARMeilleure.Instructions
{
if (op.RegisterSize == RegisterSize.Simd128)
{
Operand mask = null;
Operand mask = default;
if (op.Size < 3)
{

8
ARMeilleure/Instructions/InstEmitSimdMove32.cs
View file

@ -6,7 +6,7 @@ using System;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -267,7 +267,7 @@ namespace ARMeilleure.Instructions
Operand selectedIndex = context.ZeroExtend8(OperandType.I32, context.VectorExtract8(m, index + op.Im));
Operand inRange = context.ICompareLess(selectedIndex, Const(byteLength));
Operand elemRes = null; // Note: This is I64 for ease of calculation.
Operand elemRes = default; // Note: This is I64 for ease of calculation.
// TODO: Branching rather than conditional select.
@ -325,7 +325,7 @@ namespace ARMeilleure.Instructions
{
EmitVectorShuffleOpSimd32(context, (m, d) =>
{
Operand mask = null;
Operand mask = default;
if (op.Size < 3)
{
@ -467,7 +467,7 @@ namespace ARMeilleure.Instructions
{
if (op.RegisterSize == RegisterSize.Simd128)
{
Operand mask = null;
Operand mask = default;
if (op.Size < 3)
{

4
ARMeilleure/Instructions/InstEmitSimdShift.cs
View file

@ -9,7 +9,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{
@ -39,7 +39,7 @@ namespace ARMeilleure.Instructions
Operand dLow = context.VectorZeroUpper64(d);
Operand mask = null;
Operand mask = default;
switch (op.Size + 1)
{

2
ARMeilleure/Instructions/InstEmitSimdShift32.cs
View file

@ -8,7 +8,7 @@ using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSystem.cs
View file

@ -6,7 +6,7 @@ using System;
using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{

2
ARMeilleure/Instructions/InstEmitSystem32.cs
View file

@ -6,7 +6,7 @@ using System;
using System.Reflection;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Instructions
{