From 262b5b80541d23ed248d5b4f2220a479a35d5969 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Thu, 12 Apr 2018 16:52:00 +0200 Subject: [PATCH] Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs --- ChocolArm64/AOpCodeTable.cs | 10 +-- ChocolArm64/Instruction/AInstEmitSimdMove.cs | 35 ++++++++- Ryujinx.Tests/Cpu/CpuTestSimdMove.cs | 76 ++++++++++++++++++++ 3 files changed, 116 insertions(+), 5 deletions(-) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 3c1ec4bb..e55bccbe 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -316,6 +316,8 @@ namespace ChocolArm64 Set("01111110xx1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg)); Set("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg)); Set("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl)); + Set("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg)); + Set("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg)); Set("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg)); Set("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg)); Set("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg)); @@ -333,11 +335,11 @@ namespace ChocolArm64 Set("011111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm)); Set("0x1011110>>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm)); Set("0x1011110>>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm)); - Set("0x001110xx0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg)); - Set("0x001110xx0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg)); + Set("0>001110<<0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg)); + Set("0>001110<<0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg)); Set("0x001110<<100001001010xxxxxxxxxx", AInstEmit.Xtn_V, typeof(AOpCodeSimd)); - Set("0x001110xx0xxxxx001110xxxxxxxxxx", AInstEmit.Zip1_V, typeof(AOpCodeSimdReg)); - Set("0x001110xx0xxxxx011110xxxxxxxxxx", AInstEmit.Zip2_V, typeof(AOpCodeSimdReg)); + Set("0>001110<<0xxxxx001110xxxxxxxxxx", AInstEmit.Zip1_V, typeof(AOpCodeSimdReg)); + Set("0>001110<<0xxxxx011110xxxxxxxxxx", AInstEmit.Zip2_V, typeof(AOpCodeSimdReg)); #endregion } diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs index 80f41787..20268d58 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs @@ -256,6 +256,16 @@ namespace ChocolArm64.Instruction Context.EmitStvec(Op.Rd); } + public static void Trn1_V(AILEmitterCtx Context) + { + EmitVectorTranspose(Context, Part: 0); + } + + public static void Trn2_V(AILEmitterCtx Context) + { + EmitVectorTranspose(Context, Part: 1); + } + public static void Umov_S(AILEmitterCtx Context) { AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp; @@ -315,6 +325,29 @@ namespace ChocolArm64.Instruction } } + private static void EmitVectorTranspose(AILEmitterCtx Context, int Part) + { + AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + + int Bytes = Context.CurrOp.GetBitsCount() >> 3; + + int Elems = Bytes >> Op.Size; + + for (int Index = 0; Index < Elems; Index++) + { + int Elem = (Index & ~1) + Part; + + EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size); + + EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + } + + if (Op.RegisterSize == ARegisterSize.SIMD64) + { + EmitVectorZeroUpper(Context, Op.Rd); + } + } + private static void EmitVectorUnzip(AILEmitterCtx Context, int Part) { AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; @@ -363,4 +396,4 @@ namespace ChocolArm64.Instruction } } } -} \ No newline at end of file +} diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs b/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs index 372689d0..0681b613 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdMove.cs @@ -5,6 +5,82 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestSimdMove : CpuTest { + [Test, Description("trn1 v0.4s, v1.4s, v2.4s")] + public void Trn1_V_4S([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3, + [Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3) + { + uint Opcode = 0x4E822820; + AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 }; + AVec V2 = new AVec { W0 = B0, W1 = B1, W2 = B2, W3 = B3 }; + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(ThreadState.V0.W0, Is.EqualTo(A0)); + Assert.That(ThreadState.V0.W1, Is.EqualTo(B0)); + Assert.That(ThreadState.V0.W2, Is.EqualTo(A2)); + Assert.That(ThreadState.V0.W3, Is.EqualTo(B2)); + } + + [Test, Description("trn1 v0.8b, v1.8b, v2.8b")] + public void Trn1_V_8B([Random(2)] byte A0, [Random(1)] byte A1, [Random(2)] byte A2, [Random(1)] byte A3, + [Random(2)] byte A4, [Random(1)] byte A5, [Random(2)] byte A6, [Random(1)] byte A7, + [Random(2)] byte B0, [Random(1)] byte B1, [Random(2)] byte B2, [Random(1)] byte B3, + [Random(2)] byte B4, [Random(1)] byte B5, [Random(2)] byte B6, [Random(1)] byte B7) + { + uint Opcode = 0x0E022820; + AVec V1 = new AVec { B0 = A0, B1 = A1, B2 = A2, B3 = A3, B4 = A4, B5 = A5, B6 = A6, B7 = A7 }; + AVec V2 = new AVec { B0 = B0, B1 = B1, B2 = B2, B3 = B3, B4 = B4, B5 = B5, B6 = B6, B7 = B7 }; + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(ThreadState.V0.B0, Is.EqualTo(A0)); + Assert.That(ThreadState.V0.B1, Is.EqualTo(B0)); + Assert.That(ThreadState.V0.B2, Is.EqualTo(A2)); + Assert.That(ThreadState.V0.B3, Is.EqualTo(B2)); + Assert.That(ThreadState.V0.B4, Is.EqualTo(A4)); + Assert.That(ThreadState.V0.B5, Is.EqualTo(B4)); + Assert.That(ThreadState.V0.B6, Is.EqualTo(A6)); + Assert.That(ThreadState.V0.B7, Is.EqualTo(B6)); + } + + [Test, Description("trn2 v0.4s, v1.4s, v2.4s")] + public void Trn2_V_4S([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3, + [Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3) + { + uint Opcode = 0x4E826820; + AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 }; + AVec V2 = new AVec { W0 = B0, W1 = B1, W2 = B2, W3 = B3 }; + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(ThreadState.V0.W0, Is.EqualTo(A1)); + Assert.That(ThreadState.V0.W1, Is.EqualTo(B1)); + Assert.That(ThreadState.V0.W2, Is.EqualTo(A3)); + Assert.That(ThreadState.V0.W3, Is.EqualTo(B3)); + } + + [Test, Description("trn2 v0.8b, v1.8b, v2.8b")] + public void Trn2_V_8B([Random(1)] byte A0, [Random(2)] byte A1, [Random(1)] byte A2, [Random(2)] byte A3, + [Random(1)] byte A4, [Random(2)] byte A5, [Random(1)] byte A6, [Random(2)] byte A7, + [Random(1)] byte B0, [Random(2)] byte B1, [Random(1)] byte B2, [Random(2)] byte B3, + [Random(1)] byte B4, [Random(2)] byte B5, [Random(1)] byte B6, [Random(2)] byte B7) + { + uint Opcode = 0x0E026820; + AVec V1 = new AVec { B0 = A0, B1 = A1, B2 = A2, B3 = A3, B4 = A4, B5 = A5, B6 = A6, B7 = A7 }; + AVec V2 = new AVec { B0 = B0, B1 = B1, B2 = B2, B3 = B3, B4 = B4, B5 = B5, B6 = B6, B7 = B7 }; + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(ThreadState.V0.B0, Is.EqualTo(A1)); + Assert.That(ThreadState.V0.B1, Is.EqualTo(B1)); + Assert.That(ThreadState.V0.B2, Is.EqualTo(A3)); + Assert.That(ThreadState.V0.B3, Is.EqualTo(B3)); + Assert.That(ThreadState.V0.B4, Is.EqualTo(A5)); + Assert.That(ThreadState.V0.B5, Is.EqualTo(B5)); + Assert.That(ThreadState.V0.B6, Is.EqualTo(A7)); + Assert.That(ThreadState.V0.B7, Is.EqualTo(B7)); + } + [TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)] [TestCase(1u, 0u, 0x2313221221112010ul, 0x2717261625152414ul)] [TestCase(0u, 1u, 0x2322131221201110ul, 0x0000000000000000ul)]