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Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)

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* Added some 32 bits instructions:

* VBIC
* VTST
* VSRA

* Incremented the PTC

* Add tests and fix implementation

* Fixed VBIC immediate opcode mapping

* Hey hey!

* Nit.

Co-authored-by: gdkchan <gab.dark.100@gmail.com>
Co-authored-by: LDj3SNuD <dvitiello@gmail.com>
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
This commit is contained in:
Valentin PONS 2020-07-19 14:11:58 -04:00 • committed by GitHub
parent 9d65de74fc
commit 3af2ce74ec
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10 changed files with 361 additions and 66 deletions
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6
Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs
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@ -28,7 +28,7 @@ namespace Ryujinx.Tests.Cpu
{
0xf3000d00u, // VPADD.F32 D0, D0, D0
0xf3000f00u, // VPMAX.F32 D0, D0, D0
0xf3200f00u // VPMIN.F32 D0, D0, D0
0xf3200f00u // VPMIN.F32 D0, D0, D0
};
}
@ -41,7 +41,7 @@ namespace Ryujinx.Tests.Cpu
{
VpaddI8,
0xf2000a00u, // VPMAX.S8 D0, D0, D0
0xf2000a10u // VPMIN.S8 D0, D0, D0
0xf2000a10u // VPMIN.S8 D0, D0, D0
};
}
#endregion
@ -189,7 +189,7 @@ namespace Ryujinx.Tests.Cpu
[Explicit]
[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
public void Vadd_f32([Values(0u)] uint rd,
public void Vadd_f32([Values(0u)] uint rd,
[Values(0u, 1u)] uint rn,
[Values(0u, 2u)] uint rm,
[ValueSource("_2S_F_")] ulong z0,