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CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)

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* Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test.

* Add Clmul fast path for the 128 bits variant.

* Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant.

* Add slow path, both variants. Fix V128 Shl/Shr when shift = 0.

* A32: Add Vmull_I P64 variant (slow path); not tested.

* A32: Add Vmull_I_P8_P64 Test and fix P64 variant.
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LDj3SNuD 2021-01-04 23:45:54 +01:00 • committed by GitHub
parent a03ab0c4a0
commit 430ba6da65
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11 changed files with 264 additions and 25 deletions
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10
ARMeilleure/State/V128.cs
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@ -189,6 +189,11 @@ namespace ARMeilleure.State
/// </remarks>
public static V128 operator <<(V128 x, int shift)
{
if (shift == 0)
{
return new V128(x._e0, x._e1);
}
ulong shiftOut = x._e0 >> (64 - shift);
return new V128(x._e0 << shift, (x._e1 << shift) | shiftOut);
@ -205,6 +210,11 @@ namespace ARMeilleure.State
/// </remarks>
public static V128 operator >>(V128 x, int shift)
{
if (shift == 0)
{
return new V128(x._e0, x._e1);
}
ulong shiftOut = x._e1 & ((1UL << shift) - 1);
return new V128((x._e0 >> shift) | (shiftOut << (64 - shift)), x._e1 >> shift);