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Only throw undefined instruction exception at execution, not at translation stage

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This commit is contained in:
gdkchan 2018-02-10 14:20:46 -03:00
parent 9f612682e0
commit 55743c0cba
28 changed files with 94 additions and 43 deletions
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2
Ryujinx/Cpu/Decoder/ADecoder.cs
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@ -161,7 +161,7 @@ namespace ChocolArm64.Decoder
AInst Inst = AOpCodeTable.GetInst(OpCode);
AOpCode DecodedOpCode = new AOpCode(AInst.Undefined, Position);
AOpCode DecodedOpCode = new AOpCode(AInst.Undefined, Position, OpCode);
if (Inst.Type != null)
{

8
Ryujinx/Cpu/Decoder/AOpCode.cs
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@ -6,14 +6,16 @@ namespace ChocolArm64.Decoder
{
class AOpCode : IAOpCode
{
public long Position { get; private set; }
public long Position { get; private set; }
public int RawOpCode { get; private set; }
public AInstEmitter Emitter { get; protected set; }
public ARegisterSize RegisterSize { get; protected set; }
public AOpCode(AInst Inst, long Position)
public AOpCode(AInst Inst, long Position, int OpCode)
{
this.Position = Position;
this.Position = Position;
this.RawOpCode = OpCode;
RegisterSize = ARegisterSize.Int64;

2
Ryujinx/Cpu/Decoder/AOpCodeAdr.cs
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@ -7,7 +7,7 @@ namespace ChocolArm64.Decoder
public int Rd { get; private set; }
public long Imm { get; private set; }
public AOpCodeAdr(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeAdr(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rd = OpCode & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeAlu.cs
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@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder
public ADataOp DataOp { get; private set; }
public AOpCodeAlu(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeAlu(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rd = (OpCode >> 0) & 0x1f;
Rn = (OpCode >> 5) & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeBImm.cs
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@ -6,6 +6,6 @@ namespace ChocolArm64.Decoder
{
public long Imm { get; protected set; }
public AOpCodeBImm(AInst Inst, long Position) : base(Inst, Position) { }
public AOpCodeBImm(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode) { }
}
}

2
Ryujinx/Cpu/Decoder/AOpCodeBImmAl.cs
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@ -4,7 +4,7 @@ namespace ChocolArm64.Decoder
{
class AOpCodeBImmAl : AOpCodeBImm
{
public AOpCodeBImmAl(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeBImmAl(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Imm = Position + ADecoderHelper.DecodeImm26_2(OpCode);
}

2
Ryujinx/Cpu/Decoder/AOpCodeBImmCmp.cs
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@ -6,7 +6,7 @@ namespace ChocolArm64.Decoder
{
public int Rt { get; private set; }
public AOpCodeBImmCmp(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeBImmCmp(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rt = OpCode & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeBImmCond.cs
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@ -6,7 +6,7 @@ namespace ChocolArm64.Decoder
{
public ACond Cond { get; private set; }
public AOpCodeBImmCond(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeBImmCond(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
int O0 = (OpCode >> 4) & 1;

2
Ryujinx/Cpu/Decoder/AOpCodeBImmTest.cs
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@ -7,7 +7,7 @@ namespace ChocolArm64.Decoder
public int Rt { get; private set; }
public int Pos { get; private set; }
public AOpCodeBImmTest(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeBImmTest(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rt = OpCode & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeBReg.cs
View file

@ -6,7 +6,7 @@ namespace ChocolArm64.Decoder
{
public int Rn { get; private set; }
public AOpCodeBReg(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeBReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
int Op4 = (OpCode >> 0) & 0x1f;
int Op2 = (OpCode >> 16) & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeException.cs
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@ -6,7 +6,7 @@ namespace ChocolArm64.Decoder
{
public int Id { get; private set; }
public AOpCodeException(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeException(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Id = (OpCode >> 5) & 0xffff;
}

2
Ryujinx/Cpu/Decoder/AOpCodeMem.cs
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@ -9,7 +9,7 @@ namespace ChocolArm64.Decoder
public int Size { get; protected set; }
public bool Extend64 { get; protected set; }
public AOpCodeMem(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeMem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rt = (OpCode >> 0) & 0x1f;
Rn = (OpCode >> 5) & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeMemLit.cs
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@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder
public bool Signed { get; private set; }
public bool Prefetch { get; private set; }
public AOpCodeMemLit(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeMemLit(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rt = OpCode & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeMov.cs
View file

@ -9,7 +9,7 @@ namespace ChocolArm64.Decoder
public long Imm { get; private set; }
public int Pos { get; private set; }
public AOpCodeMov(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeMov(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
int P1 = (OpCode >> 22) & 1;
int SF = (OpCode >> 31) & 1;

2
Ryujinx/Cpu/Decoder/AOpCodeSimd.cs
View file

@ -12,7 +12,7 @@ namespace ChocolArm64.Decoder
public int SizeF => Size & 1;
public AOpCodeSimd(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSimd(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rd = (OpCode >> 0) & 0x1f;
Rn = (OpCode >> 5) & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeSimdFmov.cs
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@ -8,7 +8,7 @@ namespace ChocolArm64.Decoder
public long Imm { get; private set; }
public int Size { get; private set; }
public AOpCodeSimdFmov(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSimdFmov(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
int Imm5 = (OpCode >> 5) & 0x1f;
int Type = (OpCode >> 22) & 0x3;

2
Ryujinx/Cpu/Decoder/AOpCodeSimdImm.cs
View file

@ -9,7 +9,7 @@ namespace ChocolArm64.Decoder
public long Imm { get; private set; }
public int Size { get; private set; }
public AOpCodeSimdImm(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSimdImm(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rd = OpCode & 0x1f;

2
Ryujinx/Cpu/Decoder/AOpCodeSimdMemLit.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder
public bool Signed => false;
public bool Prefetch => false;
public AOpCodeSimdMemLit(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSimdMemLit(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
int Opc = (OpCode >> 30) & 3;

2
Ryujinx/Cpu/Decoder/AOpCodeSimdMemMs.cs
View file

@ -14,7 +14,7 @@ namespace ChocolArm64.Decoder
public int Elems { get; private set; }
public bool WBack { get; private set; }
public AOpCodeSimdMemMs(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSimdMemMs(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
switch ((OpCode >> 12) & 0xf)
{

2
Ryujinx/Cpu/Decoder/AOpCodeSimdMemSs.cs
View file

@ -14,7 +14,7 @@ namespace ChocolArm64.Decoder
public bool Replicate { get; private set; }
public bool WBack { get; private set; }
public AOpCodeSimdMemSs(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSimdMemSs(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
int Size = (OpCode >> 10) & 3;
int S = (OpCode >> 12) & 1;

2
Ryujinx/Cpu/Decoder/AOpCodeSystem.cs
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@ -11,7 +11,7 @@ namespace ChocolArm64.Decoder
public int Op1 { get; private set; }
public int Op0 { get; private set; }
public AOpCodeSystem(AInst Inst, long Position, int OpCode) : base(Inst, Position)
public AOpCodeSystem(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
Rt = (OpCode >> 0) & 0x1f;
Op2 = (OpCode >> 5) & 0x7;