Implement JIT Arm64 backend (#4114)
* Implement JIT Arm64 backend * PPTC version bump * Address some feedback from Arm64 JIT PR * Address even more PR feedback * Remove unused IsPageAligned function * Sync Qc flag before calls * Fix comment and remove unused enum * Address riperiperi PR feedback * Delete Breakpoint IR instruction that was only implemented for Arm64
This commit is contained in:
gdkchan
GitHub
parent
d16288a2a8
commit
5e0f8e8738
61 changed files with 10266 additions and 642 deletions
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@ -164,7 +164,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtas_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtasGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearestAway, isFixed: false);
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}
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@ -176,7 +180,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtas_S(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FcvtasS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearestAway, scalar: true);
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}
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@ -188,7 +196,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtas_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtasS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearestAway, scalar: false);
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}
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@ -200,7 +212,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtau_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtauGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvtu_Gp(context, FPRoundingMode.ToNearestAway, isFixed: false);
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}
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@ -212,7 +228,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtau_S(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FcvtauS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearestAway, scalar: true);
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}
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@ -224,7 +244,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtau_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtauV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearestAway, scalar: false);
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}
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@ -240,7 +264,11 @@ namespace ARMeilleure.Instructions
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int sizeF = op.Size & 1;
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if (Optimizations.UseSse2 && sizeF == 1)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtlV);
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}
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else if (Optimizations.UseSse2 && sizeF == 1)
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{
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Operand n = GetVec(op.Rn);
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@ -296,7 +324,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtms_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtmsGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
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}
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@ -308,7 +340,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtms_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtmsV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsMinusInfinity, scalar: false);
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}
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@ -320,7 +356,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtmu_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtmuGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsMinusInfinity, isFixed: false);
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}
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@ -336,7 +376,11 @@ namespace ARMeilleure.Instructions
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int sizeF = op.Size & 1;
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if (Optimizations.UseSse2 && sizeF == 1)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOpFRd(context, Intrinsic.Arm64FcvtnV);
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}
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else if (Optimizations.UseSse2 && sizeF == 1)
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{
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Operand d = GetVec(op.Rd);
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@ -405,7 +449,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtns_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtnsGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvts_Gp(context, FPRoundingMode.ToNearest, isFixed: false);
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}
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@ -417,7 +465,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtns_S(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FcvtnsS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: true);
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}
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@ -429,7 +481,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtns_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtnsV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.ToNearest, scalar: false);
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}
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@ -441,7 +497,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtnu_S(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FcvtnuS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: true);
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}
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@ -453,7 +513,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtnu_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtnuV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.ToNearest, scalar: false);
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}
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@ -465,7 +529,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtps_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtpsGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
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}
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@ -477,7 +545,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtpu_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtpuGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsPlusInfinity, isFixed: false);
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}
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@ -489,7 +561,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzs_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtzsGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
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}
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@ -501,7 +577,13 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzs_Gp_Fixed(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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InstEmitSimdHelperArm64.EmitScalarConvertBinaryOpFToGp(context, Intrinsic.Arm64FcvtzsGpFixed, op.FBits);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvts_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
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}
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@ -513,7 +595,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzs_S(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FcvtzsS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: true);
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}
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@ -525,7 +611,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzs_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtzsV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
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}
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@ -537,7 +627,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzs_V_Fixed(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorConvertBinaryOpF(context, Intrinsic.Arm64FcvtzsVFixed, GetFBits(context));
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtsOpF(context, FPRoundingMode.TowardsZero, scalar: false);
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}
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@ -549,7 +643,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzu_Gp(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFToGp(context, Intrinsic.Arm64FcvtzuGp);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: false);
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}
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@ -561,7 +659,13 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzu_Gp_Fixed(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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InstEmitSimdHelperArm64.EmitScalarConvertBinaryOpFToGp(context, Intrinsic.Arm64FcvtzuGpFixed, op.FBits);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41Fcvtu_Gp(context, FPRoundingMode.TowardsZero, isFixed: true);
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}
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@ -573,7 +677,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzu_S(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64FcvtzuS);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: true);
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}
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@ -585,7 +693,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzu_V(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64FcvtzuV);
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
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}
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@ -597,7 +709,11 @@ namespace ARMeilleure.Instructions
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public static void Fcvtzu_V_Fixed(ArmEmitterContext context)
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{
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if (Optimizations.UseSse41)
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if (Optimizations.UseAdvSimd)
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{
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InstEmitSimdHelperArm64.EmitVectorConvertBinaryOpF(context, Intrinsic.Arm64FcvtzuVFixed, GetFBits(context));
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}
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else if (Optimizations.UseSse41)
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{
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EmitSse41FcvtuOpF(context, FPRoundingMode.TowardsZero, scalar: false);
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}
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@ -609,41 +725,59 @@ namespace ARMeilleure.Instructions
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public static void Scvtf_Gp(ArmEmitterContext context)
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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Operand res = GetIntOrZR(context, op.Rn);
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if (op.RegisterSize == RegisterSize.Int32)
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if (Optimizations.UseAdvSimd)
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{
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res = context.SignExtend32(OperandType.I64, res);
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InstEmitSimdHelperArm64.EmitScalarUnaryOpFFromGp(context, Intrinsic.Arm64ScvtfGp);
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}
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else
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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res = EmitFPConvert(context, res, op.Size, signed: true);
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Operand res = GetIntOrZR(context, op.Rn);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
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if (op.RegisterSize == RegisterSize.Int32)
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{
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res = context.SignExtend32(OperandType.I64, res);
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}
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res = EmitFPConvert(context, res, op.Size, signed: true);
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context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
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}
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}
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public static void Scvtf_Gp_Fixed(ArmEmitterContext context)
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{
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OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
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Operand res = GetIntOrZR(context, op.Rn);
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if (op.RegisterSize == RegisterSize.Int32)
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if (Optimizations.UseAdvSimd)
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{
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res = context.SignExtend32(OperandType.I64, res);
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InstEmitSimdHelperArm64.EmitScalarConvertBinaryOpFFromGp(context, Intrinsic.Arm64ScvtfGpFixed, op.FBits);
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}
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else
|
||||
{
|
||||
Operand res = GetIntOrZR(context, op.Rn);
|
||||
|
||||
res = EmitFPConvert(context, res, op.Size, signed: true);
|
||||
if (op.RegisterSize == RegisterSize.Int32)
|
||||
{
|
||||
res = context.SignExtend32(OperandType.I64, res);
|
||||
}
|
||||
|
||||
res = EmitI2fFBitsMul(context, res, op.FBits);
|
||||
res = EmitFPConvert(context, res, op.Size, signed: true);
|
||||
|
||||
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
|
||||
res = EmitI2fFBitsMul(context, res, op.FBits);
|
||||
|
||||
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Scvtf_S(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64ScvtfS);
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2ScvtfOp(context, scalar: true);
|
||||
}
|
||||
|
|
@ -655,7 +789,11 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Scvtf_S_Fixed(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitScalarConvertBinaryOpF(context, Intrinsic.Arm64ScvtfSFixed, GetFBits(context));
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2ScvtfOp(context, scalar: true);
|
||||
}
|
||||
|
|
@ -667,7 +805,11 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Scvtf_V(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64ScvtfV);
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2ScvtfOp(context, scalar: false);
|
||||
}
|
||||
|
|
@ -679,7 +821,11 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Scvtf_V_Fixed(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitVectorConvertBinaryOpF(context, Intrinsic.Arm64ScvtfVFixed, GetFBits(context));
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2ScvtfOp(context, scalar: false);
|
||||
}
|
||||
|
|
@ -691,31 +837,49 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Ucvtf_Gp(ArmEmitterContext context)
|
||||
{
|
||||
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitScalarUnaryOpFFromGp(context, Intrinsic.Arm64UcvtfGp);
|
||||
}
|
||||
else
|
||||
{
|
||||
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
|
||||
|
||||
Operand res = GetIntOrZR(context, op.Rn);
|
||||
Operand res = GetIntOrZR(context, op.Rn);
|
||||
|
||||
res = EmitFPConvert(context, res, op.Size, signed: false);
|
||||
res = EmitFPConvert(context, res, op.Size, signed: false);
|
||||
|
||||
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
|
||||
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Ucvtf_Gp_Fixed(ArmEmitterContext context)
|
||||
{
|
||||
OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp;
|
||||
|
||||
Operand res = GetIntOrZR(context, op.Rn);
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitScalarConvertBinaryOpFFromGp(context, Intrinsic.Arm64UcvtfGpFixed, op.FBits);
|
||||
}
|
||||
else
|
||||
{
|
||||
Operand res = GetIntOrZR(context, op.Rn);
|
||||
|
||||
res = EmitFPConvert(context, res, op.Size, signed: false);
|
||||
res = EmitFPConvert(context, res, op.Size, signed: false);
|
||||
|
||||
res = EmitI2fFBitsMul(context, res, op.FBits);
|
||||
res = EmitI2fFBitsMul(context, res, op.FBits);
|
||||
|
||||
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
|
||||
context.Copy(GetVec(op.Rd), context.VectorInsert(context.VectorZero(), res, 0));
|
||||
}
|
||||
}
|
||||
|
||||
public static void Ucvtf_S(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitScalarUnaryOpF(context, Intrinsic.Arm64UcvtfS);
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2UcvtfOp(context, scalar: true);
|
||||
}
|
||||
|
|
@ -727,7 +891,11 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Ucvtf_S_Fixed(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitScalarConvertBinaryOpF(context, Intrinsic.Arm64UcvtfSFixed, GetFBits(context));
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2UcvtfOp(context, scalar: true);
|
||||
}
|
||||
|
|
@ -739,7 +907,11 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Ucvtf_V(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitVectorUnaryOpF(context, Intrinsic.Arm64UcvtfV);
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2UcvtfOp(context, scalar: false);
|
||||
}
|
||||
|
|
@ -751,7 +923,11 @@ namespace ARMeilleure.Instructions
|
|||
|
||||
public static void Ucvtf_V_Fixed(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
if (Optimizations.UseAdvSimd)
|
||||
{
|
||||
InstEmitSimdHelperArm64.EmitVectorConvertBinaryOpF(context, Intrinsic.Arm64UcvtfVFixed, GetFBits(context));
|
||||
}
|
||||
else if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitSse2UcvtfOp(context, scalar: false);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue