Add ATOMS, LDS, POPC, RED, STS and VOTE shader instructions, start changing the way how global memory is handled

Ryujinx.Graphics.Shader/Decoders/AtomicOp.cs

@@ -0,0 +1,15 @@
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    enum AtomicOp
+    {
+        Add                = 0,
+        Minimum            = 1,
+        Maximum            = 2,
+        Increment          = 3,
+        Decrement          = 4,
+        BitwiseAnd         = 5,
+        BitwiseOr          = 6,
+        BitwiseExclusiveOr = 7,
+        Swap               = 8
+    }
+}

Ryujinx.Graphics.Shader/Decoders/IOpCodeAlu.cs

@@ -1,10 +1,7 @@
 namespace Ryujinx.Graphics.Shader.Decoders
 {
-    interface IOpCodeAlu : IOpCodeRd, IOpCodeRa
+    interface IOpCodeAlu : IOpCodeRd, IOpCodeRa, IOpCodePredicate39
     {
-        Register Predicate39 { get; }
-
-        bool InvertP     { get; }
         bool Extended    { get; }
         bool SetCondCode { get; }
         bool Saturate    { get; }

Ryujinx.Graphics.Shader/Decoders/IOpCodePredicate39.cs

@@ -0,0 +1,9 @@
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    interface IOpCodePredicate39
+    {
+        Register Predicate39 { get; }
+
+        bool InvertP { get; }
+    }
+}

Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs

@@ -0,0 +1,39 @@
+using Ryujinx.Graphics.Shader.Instructions;
+
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    class OpCodeAtom : OpCode, IOpCodeRd, IOpCodeRa, IOpCodeReg
+    {
+        public Register Rd { get; }
+        public Register Ra { get; }
+        public Register Rb { get; }
+
+        public ReductionType Type { get; }
+
+        public int Offset { get; }
+
+        public bool Extended { get; }
+
+        public AtomicOp AtomicOp { get; }
+
+        public OpCodeAtom(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
+        {
+            Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
+            Ra = new Register(opCode.Extract(8,  8), RegisterType.Gpr);
+            Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
+
+            Type = (ReductionType)opCode.Extract(28, 2);
+
+            if (Type == ReductionType.FP32FtzRn)
+            {
+                Type = ReductionType.S64;
+            }
+
+            Offset = opCode.Extract(30, 22);
+
+            Extended = opCode.Extract(48);
+
+            AtomicOp = (AtomicOp)opCode.Extract(52, 4);
+        }
+    }
+}

Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs

@@ -0,0 +1,32 @@
+using Ryujinx.Graphics.Shader.Instructions;
+
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    class OpCodeRed : OpCode, IOpCodeRd, IOpCodeRa
+    {
+        public Register Rd { get; }
+        public Register Ra { get; }
+
+        public AtomicOp AtomicOp { get; }
+
+        public ReductionType Type { get; }
+
+        public int Offset { get; }
+
+        public bool Extended { get; }
+
+        public OpCodeRed(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
+        {
+            Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
+            Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr);
+
+            Type = (ReductionType)opCode.Extract(20, 3);
+
+            AtomicOp = (AtomicOp)opCode.Extract(23, 3);
+
+            Offset = opCode.Extract(28, 20);
+
+            Extended = opCode.Extract(48);
+        }
+    }
+}

Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs

@@ -32,6 +32,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
 #region Instructions
             Set("1110111111011x", InstEmit.Ald,     typeof(OpCodeAttribute));
             Set("1110111111110x", InstEmit.Ast,     typeof(OpCodeAttribute));
+            Set("11101100xxxxxx", InstEmit.Atoms,   typeof(OpCodeAtom));
             Set("0100110000000x", InstEmit.Bfe,     typeof(OpCodeAluCbuf));
             Set("0011100x00000x", InstEmit.Bfe,     typeof(OpCodeAluImm));
             Set("0101110000000x", InstEmit.Bfe,     typeof(OpCodeAluReg));
@@ -122,6 +123,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
             Set("1110111101000x", InstEmit.Ld,      typeof(OpCodeMemory));
             Set("1110111110010x", InstEmit.Ldc,     typeof(OpCodeLdc));
             Set("1110111011010x", InstEmit.Ldg,     typeof(OpCodeMemory));
+            Set("1110111101001x", InstEmit.Lds,     typeof(OpCodeMemory));
             Set("0100110001000x", InstEmit.Lop,     typeof(OpCodeLopCbuf));
             Set("0011100001000x", InstEmit.Lop,     typeof(OpCodeLopImm));
             Set("000001xxxxxxxx", InstEmit.Lop,     typeof(OpCodeLopImm32));
@@ -136,7 +138,11 @@ namespace Ryujinx.Graphics.Shader.Decoders
             Set("0101000010000x", InstEmit.Mufu,    typeof(OpCodeFArith));
             Set("1111101111100x", InstEmit.Out,     typeof(OpCode));
             Set("111000101010xx", InstEmit.Pbk,     typeof(OpCodeSsy));
+            Set("0100110000001x", InstEmit.Popc,    typeof(OpCodeAluCbuf));
+            Set("0011100x00001x", InstEmit.Popc,    typeof(OpCodeAluImm));
+            Set("0101110000001x", InstEmit.Popc,    typeof(OpCodeAluReg));
             Set("0101000010010x", InstEmit.Psetp,   typeof(OpCodePsetp));
+            Set("1110101111111x", InstEmit.Red,     typeof(OpCodeRed));
             Set("0100110010010x", InstEmit.Rro,     typeof(OpCodeFArithCbuf));
             Set("0011100x10010x", InstEmit.Rro,     typeof(OpCodeFArithImm));
             Set("0101110010010x", InstEmit.Rro,     typeof(OpCodeFArithReg));
@@ -154,6 +160,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
             Set("111000101001xx", InstEmit.Ssy,     typeof(OpCodeSsy));
             Set("1110111101010x", InstEmit.St,      typeof(OpCodeMemory));
             Set("1110111011011x", InstEmit.Stg,     typeof(OpCodeMemory));
+            Set("1110111101011x", InstEmit.Sts,     typeof(OpCodeMemory));
             Set("11101011001xxx", InstEmit.Sust,    typeof(OpCodeImage));
             Set("1111000011111x", InstEmit.Sync,    typeof(OpCodeSync));
             Set("110000xxxx111x", InstEmit.Tex,     typeof(OpCodeTex));
@@ -168,6 +175,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
             Set("1101111101001x", InstEmit.Txq,     typeof(OpCodeTex));
             Set("1101111101010x", InstEmit.TxqB,    typeof(OpCodeTex));
             Set("01011111xxxxxx", InstEmit.Vmad,    typeof(OpCodeVideo));
+            Set("0101000011011x", InstEmit.Vote,    typeof(OpCodeVote));
             Set("0100111xxxxxxx", InstEmit.Xmad,    typeof(OpCodeAluCbuf));
             Set("0011011x00xxxx", InstEmit.Xmad,    typeof(OpCodeAluImm));
             Set("010100010xxxxx", InstEmit.Xmad,    typeof(OpCodeAluRegCbuf));

Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs

@@ -0,0 +1,26 @@
+using Ryujinx.Graphics.Shader.Instructions;
+
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    class OpCodeVote : OpCode, IOpCodeRd, IOpCodePredicate39
+    {
+        public Register Rd          { get; }
+        public Register Predicate39 { get; }
+        public Register Predicate45 { get; }
+
+        public VoteOp VoteOp { get; }
+
+        public bool InvertP { get; }
+
+        public OpCodeVote(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
+        {
+            Rd          = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
+            Predicate39 = new Register(opCode.Extract(39, 3), RegisterType.Predicate);
+            Predicate45 = new Register(opCode.Extract(45, 3), RegisterType.Predicate);
+
+            InvertP = opCode.Extract(42);
+
+            VoteOp = (VoteOp)opCode.Extract(48, 2);
+        }
+    }
+}

Ryujinx.Graphics.Shader/Decoders/ReductionType.cs

@@ -0,0 +1,12 @@
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    enum ReductionType
+    {
+        U32       = 0,
+        S32       = 1,
+        U64       = 2,
+        FP32FtzRn = 3,
+        U128      = 4,
+        S64       = 5
+    }
+}

Ryujinx.Graphics.Shader/Decoders/SystemRegister.cs

@@ -2,6 +2,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
 {
     enum SystemRegister
     {
+        LaneId     = 0,
         YDirection = 0x12,
         ThreadId   = 0x20,
         ThreadIdX  = 0x21,
@@ -9,6 +10,11 @@ namespace Ryujinx.Graphics.Shader.Decoders
         ThreadIdZ  = 0x23,
         CtaIdX     = 0x25,
         CtaIdY     = 0x26,
-        CtaIdZ     = 0x27
+        CtaIdZ     = 0x27,
+        EqMask     = 0x38,
+        LtMask     = 0x39,
+        LeMask     = 0x3a,
+        GtMask     = 0x3b,
+        GeMask     = 0x3c
     }
 }

Ryujinx.Graphics.Shader/Decoders/VoteOp.cs

@@ -0,0 +1,9 @@
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    enum VoteOp
+    {
+        All      = 0,
+        Any      = 1,
+        AllEqual = 2
+    }
+}