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Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)

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* Implement VMOVL and VORR.I32 AArch32 SIMD instructions

* Rename <dt> to <size> on test description

* Rename Widen to Long and improve VMOVL implementation a bit
This commit is contained in:
gdkchan 2020-03-10 02:17:30 -03:00 • committed by GitHub
parent 08c0e3829b
commit 89ccec197e
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GPG key ID: 4AEE18F83AFDEB23
9 changed files with 165 additions and 7 deletions
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39
ARMeilleure/Instructions/InstEmitSimdLogical32.cs
View file

@ -2,7 +2,10 @@
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper;
using static ARMeilleure.Instructions.InstEmitSimdHelper32;
using static ARMeilleure.IntermediateRepresentation.OperandHelper;
namespace ARMeilleure.Instructions
{
@ -64,6 +67,42 @@ namespace ARMeilleure.Instructions
}
}
public static void Vorr_II(ArmEmitterContext context)
{
OpCode32SimdImm op = (OpCode32SimdImm)context.CurrOp;
long immediate = op.Immediate;
// Replicate fields to fill the 64-bits, if size is < 64-bits.
switch (op.Size)
{
case 0: immediate *= 0x0101010101010101L; break;
case 1: immediate *= 0x0001000100010001L; break;
case 2: immediate *= 0x0000000100000001L; break;
}
Operand imm = Const(immediate);
Operand res = GetVecA32(op.Qd);
if (op.Q)
{
for (int elem = 0; elem < 2; elem++)
{
Operand de = EmitVectorExtractZx(context, op.Qd, elem, 3);
res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), elem, 3);
}
}
else
{
Operand de = EmitVectorExtractZx(context, op.Qd, op.Vd & 1, 3);
res = EmitVectorInsert(context, res, context.BitwiseOr(de, imm), op.Vd & 1, 3);
}
context.Copy(GetVecA32(op.Qd), res);
}
private static void EmitBifBit(ArmEmitterContext context, bool notRm)
{
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;

30
ARMeilleure/Instructions/InstEmitSimdMove32.cs
View file

@ -139,6 +139,36 @@ namespace ARMeilleure.Instructions
}
}
public static void Vmovl(ArmEmitterContext context)
{
OpCode32SimdLong op = (OpCode32SimdLong)context.CurrOp;
Operand res = context.VectorZero();
int elems = op.GetBytesCount() >> op.Size;
for (int index = 0; index < elems; index++)
{
Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, !op.U);
if (op.Size == 2)
{
if (op.U)
{
me = context.ZeroExtend32(OperandType.I64, me);
}
else
{
me = context.SignExtend32(OperandType.I64, me);
}
}
res = EmitVectorInsert(context, res, me, index, op.Size + 1);
}
context.Copy(GetVecA32(op.Qd), res);
}
public static void Vtbl(ArmEmitterContext context)
{
OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;

4
ARMeilleure/Instructions/InstName.cs
View file

@ -81,7 +81,7 @@ namespace ARMeilleure.Instructions
Sdiv,
Smaddl,
Smsubl,
Smul__,
Smulh,
Smull,
Smulw_,
Ssat,
@ -500,6 +500,7 @@ namespace ARMeilleure.Instructions
Smlaw_,
Smmla,
Smmls,
Smul__,
Smmul,
Stl,
Stlb,
@ -560,6 +561,7 @@ namespace ARMeilleure.Instructions
Vmla,
Vmls,
Vmov,
Vmovl,
Vmovn,
Vmrs,
Vmsr,