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Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)

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* Implement VMOVL and VORR.I32 AArch32 SIMD instructions

* Rename <dt> to <size> on test description

* Rename Widen to Long and improve VMOVL implementation a bit
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gdkchan 2020-03-10 02:17:30 -03:00 • committed by GitHub
parent 08c0e3829b
commit 89ccec197e
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9 changed files with 165 additions and 7 deletions
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28
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
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@ -56,6 +56,34 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")]
public void Vorr_II([Range(0u, 4u)] uint rd,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] byte imm,
[Values(0u, 1u, 2u, 3u)] uint cMode,
[Values] bool q)
{
uint opcode = 0xf2800110u; // VORR.I32 D0, #0
if (q)
{
opcode |= 1 << 6;
rd <<= 1;
}
opcode |= (uint)(imm & 0xf) << 0;
opcode |= (uint)(imm & 0x70) << 12;
opcode |= (uint)(imm & 0x80) << 17;
opcode |= (cMode & 0x3) << 9;
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
#endif
}
}