Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions * Rename <dt> to <size> on test description * Rename Widen to Long and improve VMOVL implementation a bit
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9 changed files with 165 additions and 7 deletions
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@ -56,6 +56,34 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")]
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public void Vorr_II([Range(0u, 4u)] uint rd,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] byte imm,
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[Values(0u, 1u, 2u, 3u)] uint cMode,
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[Values] bool q)
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{
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uint opcode = 0xf2800110u; // VORR.I32 D0, #0
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if (q)
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{
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opcode |= 1 << 6;
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rd <<= 1;
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}
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opcode |= (uint)(imm & 0xf) << 0;
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opcode |= (uint)(imm & 0x70) << 12;
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opcode |= (uint)(imm & 0x80) << 17;
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opcode |= (cMode & 0x3) << 9;
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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V128 v0 = MakeVectorE0E1(z, z);
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SingleOpcode(opcode, v0: v0);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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