mirrors/ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)

Browse source 
* Add files via upload

* Add files via upload

* Add files via upload

* CPE

* Add EmitSse42Crc32()

* Update CpuTestSimdCmp.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update Instructions.cs
This commit is contained in:
LDj3SNuD 2018-06-26 03:32:29 +02:00 • committed by gdkchan
parent 37a6e84fd4
commit 8f6387128a
13 changed files with 698 additions and 120 deletions
Download patch file Download diff file Expand all files Collapse all files

64
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -3,6 +3,7 @@ using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
using System.Reflection;
using System.Runtime.CompilerServices;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.X86;
@ -34,11 +35,27 @@ namespace ChocolArm64.Instruction
return (8 << (Op.Size + 1)) - Op.Imm;
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static void EmitSse2Call(AILEmitterCtx Context, string Name)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
EmitSseCall(Context, Name, typeof(Sse2));
}
int SizeF = Op.Size & 1;
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static void EmitSse41Call(AILEmitterCtx Context, string Name)
{
EmitSseCall(Context, Name, typeof(Sse41));
}
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static void EmitSse42Call(AILEmitterCtx Context, string Name)
{
EmitSseCall(Context, Name, typeof(Sse42));
}
private static void EmitSseCall(AILEmitterCtx Context, string Name, Type Type)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
void Ldvec(int Reg)
{
@ -57,8 +74,6 @@ namespace ChocolArm64.Instruction
Type BaseType = null;
Type[] Types;
switch (Op.Size)
{
case 0: BaseType = typeof(Vector128<sbyte>); break;
@ -71,15 +86,13 @@ namespace ChocolArm64.Instruction
{
Ldvec(BinOp.Rm);
Types = new Type[] { BaseType, BaseType };
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
}
else
{
Types = new Type[] { BaseType };
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
}
Context.EmitCall(typeof(Sse2).GetMethod(Name, Types));
switch (Op.Size)
{
case 0: AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorSByteToSingle)); break;
@ -96,7 +109,7 @@ namespace ChocolArm64.Instruction
}
}
public static void EmitSse2CallF(AILEmitterCtx Context, string Name)
public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
@ -114,36 +127,31 @@ namespace ChocolArm64.Instruction
Ldvec(Op.Rn);
Type BaseType = SizeF == 0
? typeof(Vector128<float>)
: typeof(Vector128<double>);
Type Type;
Type BaseType;
Type[] Types;
if (SizeF == 0)
{
Type = typeof(Sse);
BaseType = typeof(Vector128<float>);
}
else /* if (SizeF == 1) */
{
Type = typeof(Sse2);
BaseType = typeof(Vector128<double>);
}
if (Op is AOpCodeSimdReg BinOp)
{
Ldvec(BinOp.Rm);
Types = new Type[] { BaseType, BaseType };
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType, BaseType }));
}
else
{
Types = new Type[] { BaseType };
Context.EmitCall(Type.GetMethod(Name, new Type[] { BaseType }));
}
MethodInfo MthdInfo;
if (SizeF == 0)
{
MthdInfo = typeof(Sse).GetMethod(Name, Types);
}
else /* if (SizeF == 1) */
{
MthdInfo = typeof(Sse2).GetMethod(Name, Types);
}
Context.EmitCall(MthdInfo);
if (SizeF == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorDoubleToSingle));