Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
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parent
e174100474
commit
950011c90f
20 changed files with 217 additions and 93 deletions
7
ChocolArm64/Translation/AILBarrier.cs
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7
ChocolArm64/Translation/AILBarrier.cs
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@ -0,0 +1,7 @@
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namespace ChocolArm64.Translation
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{
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struct AILBarrier : IAILEmit
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{
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public void Emit(AILEmitter Context) { }
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}
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}
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@ -4,11 +4,13 @@ namespace ChocolArm64.Translation
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{
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class AILBlock : IAILEmit
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{
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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public long IntInputs { get; private set; }
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public long IntOutputs { get; private set; }
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public long IntAwOutputs { get; private set; }
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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public long VecInputs { get; private set; }
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public long VecOutputs { get; private set; }
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public long VecAwOutputs { get; private set; }
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public bool HasStateStore { get; private set; }
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@ -24,13 +26,22 @@ namespace ChocolArm64.Translation
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public void Add(IAILEmit ILEmitter)
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{
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if (ILEmitter is AILOpCodeLoad Ld && AILEmitter.IsRegIndex(Ld.Index))
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if (ILEmitter is AILBarrier)
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{
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//Those barriers are used to separate the groups of CIL
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//opcodes emitted by each ARM instruction.
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//We can only consider the new outputs for doing input elimination
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//after all the CIL opcodes used by the instruction being emitted.
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IntAwOutputs = IntOutputs;
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VecAwOutputs = VecOutputs;
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}
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else if (ILEmitter is AILOpCodeLoad Ld && AILEmitter.IsRegIndex(Ld.Index))
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{
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switch (Ld.IoType)
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{
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case AIoType.Flag: IntInputs |= ((1L << Ld.Index) << 32) & ~IntOutputs; break;
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case AIoType.Int: IntInputs |= (1L << Ld.Index) & ~IntOutputs; break;
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case AIoType.Vector: VecInputs |= (1L << Ld.Index) & ~VecOutputs; break;
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case AIoType.Flag: IntInputs |= ((1L << Ld.Index) << 32) & ~IntAwOutputs; break;
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case AIoType.Int: IntInputs |= (1L << Ld.Index) & ~IntAwOutputs; break;
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case AIoType.Vector: VecInputs |= (1L << Ld.Index) & ~VecAwOutputs; break;
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}
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}
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else if (ILEmitter is AILOpCodeStore St)
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@ -39,14 +39,16 @@ namespace ChocolArm64.Translation
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private const int Tmp4Index = -4;
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private const int Tmp5Index = -5;
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public AILEmitterCtx(ATranslator Translator, ABlock[] Graph, ABlock Root)
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public AILEmitterCtx(
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ATranslator Translator,
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ABlock[] Graph,
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ABlock Root,
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string SubName)
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{
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this.Translator = Translator;
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this.Graph = Graph;
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this.Root = Root;
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string SubName = $"Sub{Root.Position:X16}";
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Labels = new Dictionary<long, AILLabel>();
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Emitter = new AILEmitter(Graph, Root, SubName);
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@ -92,6 +94,8 @@ namespace ChocolArm64.Translation
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}
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CurrOp.Emitter(this);
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ILBlock.Add(new AILBarrier());
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}
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public bool TryOptEmitSubroutineCall()
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@ -11,12 +11,10 @@ namespace ChocolArm64.Translation
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public ARegisterSize RegisterSize { get; private set; }
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public AILOpCodeLoad(int Index, AIoType IoType) : this(Index, IoType, ARegisterSize.Int64) { }
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public AILOpCodeLoad(int Index, AIoType IoType, ARegisterSize RegisterSize)
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public AILOpCodeLoad(int Index, AIoType IoType, ARegisterSize RegisterSize = 0)
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{
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this.IoType = IoType;
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this.Index = Index;
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this.IoType = IoType;
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this.RegisterSize = RegisterSize;
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}
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@ -11,10 +11,10 @@ namespace ChocolArm64.Translation
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public ARegisterSize RegisterSize { get; private set; }
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public AILOpCodeStore(int Index, AIoType IoType, ARegisterSize RegisterSize = ARegisterSize.Int64)
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public AILOpCodeStore(int Index, AIoType IoType, ARegisterSize RegisterSize = 0)
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{
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this.IoType = IoType;
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this.Index = Index;
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this.IoType = IoType;
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this.RegisterSize = RegisterSize;
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}
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@ -67,7 +67,7 @@ namespace ChocolArm64.Translation
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public long VecOutputs;
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}
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private const int MaxOptGraphLength = 120;
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private const int MaxOptGraphLength = 55;
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public ALocalAlloc(AILBlock[] Graph, AILBlock Root)
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{
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@ -149,11 +149,7 @@ namespace ChocolArm64.Translation
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if (RetTarget)
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{
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BlkIO.Entry = Block;
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BlkIO.IntInputs = 0;
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BlkIO.VecInputs = 0;
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BlkIO.IntOutputs = 0;
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BlkIO.VecOutputs = 0;
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BlkIO.Entry = Block;
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}
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else
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{
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