Implement inline memory load/store exclusive and ordered (#1413)
* Implement inline memory load/store exclusive * Fix missing REX prefix on 8-bits CMPXCHG * Increment PTC version due to bugfix * Remove redundant memory checks * Address PR feedback * Increment PPTC version
This commit is contained in:
gdkchan
GitHub
parent
57bb0abda3
commit
9878fc2d3c
19 changed files with 385 additions and 376 deletions
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@ -23,7 +23,7 @@ namespace ARMeilleure.Instructions
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public static void Clrex(ArmEmitterContext context)
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{
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ClearExclusive)));
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EmitClearExclusive(context);
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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@ -139,8 +139,6 @@ namespace ARMeilleure.Instructions
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Operand t = GetIntOrZR(context, op.Rt);
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Operand s = null;
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if (pair)
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{
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Debug.Assert(op.Size == 2 || op.Size == 3, "Invalid size for pairwise store.");
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@ -159,18 +157,11 @@ namespace ARMeilleure.Instructions
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value = context.VectorInsert(value, t2, 1);
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}
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s = EmitStoreExclusive(context, address, value, exclusive, op.Size + 1);
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EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false);
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}
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else
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{
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s = EmitStoreExclusive(context, address, t, exclusive, op.Size);
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}
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if (s != null)
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{
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// This is only needed for exclusive stores. The function returns 0
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// when the store is successful, and 1 otherwise.
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SetIntOrZR(context, op.Rs, s);
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EmitStoreExclusive(context, address, t, exclusive, op.Size, op.Rs, a32: false);
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}
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}
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@ -13,7 +13,7 @@ namespace ARMeilleure.Instructions
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{
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public static void Clrex(ArmEmitterContext context)
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{
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ClearExclusive)));
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EmitClearExclusive(context);
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}
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public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
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@ -198,34 +198,21 @@ namespace ARMeilleure.Instructions
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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Operand leResult = context.BitwiseOr(lo, context.ShiftLeft(hi, Const(32)));
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Operand leS = EmitStoreExclusive(context, address, leResult, exclusive, size);
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if (exclusive)
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{
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SetIntA32(context, op.Rd, leS);
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}
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EmitStoreExclusive(context, address, leResult, exclusive, size, op.Rd, a32: true);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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Operand beResult = context.BitwiseOr(hi, context.ShiftLeft(lo, Const(32)));
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Operand beS = EmitStoreExclusive(context, address, beResult, exclusive, size);
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if (exclusive)
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{
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SetIntA32(context, op.Rd, beS);
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}
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EmitStoreExclusive(context, address, beResult, exclusive, size, op.Rd, a32: true);
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context.MarkLabel(lblEnd);
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}
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else
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{
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Operand s = EmitStoreExclusive(context, address, context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt)), exclusive, size);
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// This is only needed for exclusive stores. The function returns 0
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// when the store is successful, and 1 otherwise.
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if (exclusive)
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{
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SetIntA32(context, op.Rd, s);
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}
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Operand value = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
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EmitStoreExclusive(context, address, value, exclusive, size, op.Rd, a32: true);
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}
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}
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}
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@ -1,87 +1,180 @@
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryExHelper
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{
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public static Operand EmitLoadExclusive(
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ArmEmitterContext context,
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Operand address,
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bool exclusive,
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int size)
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{
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MethodInfo info = null;
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private const int ErgSizeLog2 = 4;
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public static Operand EmitLoadExclusive(ArmEmitterContext context, Operand address, bool exclusive, int size)
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{
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if (exclusive)
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{
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switch (size)
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Operand value;
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if (size == 4)
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{
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case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByteExclusive)); break;
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case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16Exclusive)); break;
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case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32Exclusive)); break;
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case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64Exclusive)); break;
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case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128Exclusive)); break;
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Operand isUnalignedAddr = InstEmitMemoryHelper.EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblFastPath);
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// Only 128-bit CAS is guaranteed to have a atomic load.
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Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, null, write: false);
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Operand zero = context.VectorZero();
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value = context.CompareAndSwap(physAddr, zero, zero);
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}
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else
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{
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value = InstEmitMemoryHelper.EmitReadIntAligned(context, address, size);
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}
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
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context.Store(exAddrPtr, context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask())));
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context.Store(exValuePtr, value);
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return value;
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}
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else
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{
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switch (size)
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{
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case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break;
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case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break;
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case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break;
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case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
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case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); break;
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}
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return InstEmitMemoryHelper.EmitReadIntAligned(context, address, size);
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}
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return context.Call(info, address);
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}
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public static Operand EmitStoreExclusive(
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public static void EmitStoreExclusive(
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ArmEmitterContext context,
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Operand address,
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Operand value,
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bool exclusive,
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int size)
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int size,
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int rs,
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bool a32)
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{
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if (size < 3)
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{
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value = context.ConvertI64ToI32(value);
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}
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MethodInfo info = null;
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if (exclusive)
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{
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switch (size)
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void SetRs(Operand value)
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{
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case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByteExclusive)); break;
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case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16Exclusive)); break;
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case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32Exclusive)); break;
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case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64Exclusive)); break;
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case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128Exclusive)); break;
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if (a32)
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{
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SetIntA32(context, rs, value);
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}
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else
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{
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SetIntOrZR(context, rs, value);
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}
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}
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return context.Call(info, address, value);
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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Operand exAddr = context.Load(address.Type, exAddrPtr);
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// STEP 1: Check if we have exclusive access to this memory region. If not, fail and skip store.
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Operand maskedAddress = context.BitwiseAnd(address, Const(GetExclusiveAddressMask()));
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Operand exFailed = context.ICompareNotEqual(exAddr, maskedAddress);
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Operand lblExit = Label();
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SetRs(exFailed);
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context.BranchIfTrue(lblExit, exFailed);
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// STEP 2: We have exclusive access, make sure that the address is valid.
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Operand isUnalignedAddr = InstEmitMemoryHelper.EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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// STEP 3: We have exclusive access and the address is valid, attempt the store using CAS.
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context.MarkLabel(lblFastPath);
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Operand physAddr = InstEmitMemoryHelper.EmitPtPointerLoad(context, address, null, write: true);
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Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset()));
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Operand exValue = size switch
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{
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0 => context.Load8(exValuePtr),
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1 => context.Load16(exValuePtr),
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2 => context.Load(OperandType.I32, exValuePtr),
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3 => context.Load(OperandType.I64, exValuePtr),
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_ => context.Load(OperandType.V128, exValuePtr)
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};
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Operand currValue = size switch
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{
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0 => context.CompareAndSwap8(physAddr, exValue, value),
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1 => context.CompareAndSwap16(physAddr, exValue, value),
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_ => context.CompareAndSwap(physAddr, exValue, value)
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};
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// STEP 4: Check if we succeeded by comparing expected and in-memory values.
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Operand storeFailed;
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if (size == 4)
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{
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Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0);
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Operand currValueHigh = context.VectorExtract(OperandType.I64, currValue, 1);
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Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0);
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Operand exValueHigh = context.VectorExtract(OperandType.I64, exValue, 1);
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storeFailed = context.BitwiseOr(
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context.ICompareNotEqual(currValueLow, exValueLow),
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context.ICompareNotEqual(currValueHigh, exValueHigh));
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}
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else
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{
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storeFailed = context.ICompareNotEqual(currValue, exValue);
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}
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SetRs(storeFailed);
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context.MarkLabel(lblExit);
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}
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else
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{
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switch (size)
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{
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case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break;
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case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break;
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case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break;
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case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break;
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case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); break;
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}
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context.Call(info, address, value);
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return null;
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InstEmitMemoryHelper.EmitWriteIntAligned(context, address, value, size);
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}
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}
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public static void EmitClearExclusive(ArmEmitterContext context)
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{
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Operand arg0 = context.LoadArgument(OperandType.I64, 0);
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Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset()));
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// We store ULONG max to force any exclusive address checks to fail,
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// since this value is not aligned to the ERG mask.
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context.Store(exAddrPtr, Const(ulong.MaxValue));
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}
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private static long GetExclusiveAddressMask() => ~((4L << ErgSizeLog2) - 1);
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}
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}
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@ -140,7 +140,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false);
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Operand value = null;
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@ -157,6 +157,36 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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public static Operand EmitReadIntAligned(ArmEmitterContext context, Operand address, int size)
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{
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if ((uint)size > 4)
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, null, write: false);
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return size switch
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{
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0 => context.Load8(physAddr),
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1 => context.Load16(physAddr),
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2 => context.Load(OperandType.I32, physAddr),
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3 => context.Load(OperandType.I64, physAddr),
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_ => context.Load(OperandType.V128, physAddr)
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};
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}
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private static void EmitReadVector(
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ArmEmitterContext context,
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Operand address,
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@ -181,7 +211,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false);
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Operand value = null;
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@ -222,7 +252,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true);
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Operand value = GetInt(context, rt);
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@ -242,6 +272,45 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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public static void EmitWriteIntAligned(ArmEmitterContext context, Operand address, Operand value, int size)
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{
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if ((uint)size > 4)
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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// The call is not expected to return (it should throw).
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, null, write: true);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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if (size == 0)
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{
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context.Store8(physAddr, value);
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}
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else if (size == 1)
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{
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context.Store16(physAddr, value);
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}
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else
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{
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context.Store(physAddr, value);
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}
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}
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private static void EmitWriteVector(
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ArmEmitterContext context,
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Operand address,
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@ -265,7 +334,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true);
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Operand value = GetVec(rt);
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@ -281,7 +350,7 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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private static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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public static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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{
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ulong addressCheckMask = ~((1UL << context.Memory.AddressSpaceBits) - 1);
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@ -290,7 +359,7 @@ namespace ARMeilleure.Instructions
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return context.BitwiseAnd(address, Const(address.Type, (long)addressCheckMask));
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}
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private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblSlowPath)
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public static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblSlowPath, bool write)
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{
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int ptLevelBits = context.Memory.AddressSpaceBits - 12; // 12 = Number of page bits.
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int ptLevelSize = 1 << ptLevelBits;
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@ -302,6 +371,12 @@ namespace ARMeilleure.Instructions
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int bit = PageBits;
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|
||||
// Load page table entry from the page table.
|
||||
// This was designed to support multi-level page tables of any size, however right
|
||||
// now we only use flat page tables (so there's only one level).
|
||||
// The page table entry contains the host address where the page is located.
|
||||
// Additionally, the higher 16-bits of the host address may contain extra information
|
||||
// used for write tracking, so this must be handled here aswell.
|
||||
do
|
||||
{
|
||||
Operand addrPart = context.ShiftRightUI(address, Const(bit));
|
||||
|
|
@ -326,7 +401,37 @@ namespace ARMeilleure.Instructions
|
|||
}
|
||||
while (bit < context.Memory.AddressSpaceBits);
|
||||
|
||||
context.BranchIfTrue(lblSlowPath, context.ICompareLessOrEqual(pte, Const(0L)));
|
||||
if (lblSlowPath != null)
|
||||
{
|
||||
context.BranchIfTrue(lblSlowPath, context.ICompareLessOrEqual(pte, Const(0L)));
|
||||
}
|
||||
else
|
||||
{
|
||||
// When no label is provided to jump to a slow path if the address is invalid,
|
||||
// we do the validation ourselves, and throw if needed.
|
||||
if (write)
|
||||
{
|
||||
Operand lblNotWatched = Label();
|
||||
|
||||
// Is the page currently being monitored for modifications? If so we need to call MarkRegionAsModified.
|
||||
context.BranchIfTrue(lblNotWatched, context.ICompareGreaterOrEqual(pte, Const(0L)));
|
||||
|
||||
// Mark the region as modified. Size here doesn't matter as address is assumed to be size aligned here.
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.MarkRegionAsModified)), address, Const(1UL));
|
||||
context.MarkLabel(lblNotWatched);
|
||||
}
|
||||
|
||||
Operand lblNonNull = Label();
|
||||
|
||||
// Skip exception if the PTE address is non-null (not zero).
|
||||
context.BranchIfTrue(lblNonNull, pte);
|
||||
|
||||
// The call is not expected to return (it should throw).
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.ThrowInvalidMemoryAccess)), address);
|
||||
context.MarkLabel(lblNonNull);
|
||||
|
||||
pte = context.BitwiseAnd(pte, Const(0xffffffffffffUL));
|
||||
}
|
||||
|
||||
Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, PageMask));
|
||||
|
||||
|
|
|
|||
|
|
@ -3,38 +3,29 @@ using ARMeilleure.State;
|
|||
using ARMeilleure.Translation;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
using System.Threading;
|
||||
|
||||
namespace ARMeilleure.Instructions
|
||||
{
|
||||
static class NativeInterface
|
||||
{
|
||||
private const int ErgSizeLog2 = 4;
|
||||
|
||||
private class ThreadContext
|
||||
{
|
||||
public State.ExecutionContext Context { get; }
|
||||
public ExecutionContext Context { get; }
|
||||
public IMemoryManager Memory { get; }
|
||||
public Translator Translator { get; }
|
||||
|
||||
public ulong ExclusiveAddress { get; set; }
|
||||
public ulong ExclusiveValueLow { get; set; }
|
||||
public ulong ExclusiveValueHigh { get; set; }
|
||||
|
||||
public ThreadContext(State.ExecutionContext context, IMemoryManager memory, Translator translator)
|
||||
public ThreadContext(ExecutionContext context, IMemoryManager memory, Translator translator)
|
||||
{
|
||||
Context = context;
|
||||
Memory = memory;
|
||||
Translator = translator;
|
||||
|
||||
ExclusiveAddress = ulong.MaxValue;
|
||||
}
|
||||
}
|
||||
|
||||
[ThreadStatic]
|
||||
private static ThreadContext _context;
|
||||
|
||||
public static void RegisterThread(State.ExecutionContext context, IMemoryManager memory, Translator translator)
|
||||
public static void RegisterThread(ExecutionContext context, IMemoryManager memory, Translator translator)
|
||||
{
|
||||
_context = new ThreadContext(context, memory, translator);
|
||||
}
|
||||
|
|
@ -202,63 +193,6 @@ namespace ARMeilleure.Instructions
|
|||
}
|
||||
#endregion
|
||||
|
||||
#region "Read exclusive"
|
||||
public static byte ReadByteExclusive(ulong address)
|
||||
{
|
||||
byte value = _context.Memory.Read<byte>(address);
|
||||
|
||||
_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
|
||||
_context.ExclusiveValueLow = value;
|
||||
_context.ExclusiveValueHigh = 0;
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
public static ushort ReadUInt16Exclusive(ulong address)
|
||||
{
|
||||
ushort value = _context.Memory.Read<ushort>(address);
|
||||
|
||||
_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
|
||||
_context.ExclusiveValueLow = value;
|
||||
_context.ExclusiveValueHigh = 0;
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
public static uint ReadUInt32Exclusive(ulong address)
|
||||
{
|
||||
uint value = _context.Memory.Read<uint>(address);
|
||||
|
||||
_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
|
||||
_context.ExclusiveValueLow = value;
|
||||
_context.ExclusiveValueHigh = 0;
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
public static ulong ReadUInt64Exclusive(ulong address)
|
||||
{
|
||||
ulong value = _context.Memory.Read<ulong>(address);
|
||||
|
||||
_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
|
||||
_context.ExclusiveValueLow = value;
|
||||
_context.ExclusiveValueHigh = 0;
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
public static V128 ReadVector128Exclusive(ulong address)
|
||||
{
|
||||
V128 value = MemoryManagerPal.AtomicLoad128(ref _context.Memory.GetRef<V128>(address));
|
||||
|
||||
_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
|
||||
_context.ExclusiveValueLow = value.Extract<ulong>(0);
|
||||
_context.ExclusiveValueHigh = value.Extract<ulong>(1);
|
||||
|
||||
return value;
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "Write"
|
||||
public static void WriteByte(ulong address, byte value)
|
||||
{
|
||||
|
|
@ -286,122 +220,14 @@ namespace ARMeilleure.Instructions
|
|||
}
|
||||
#endregion
|
||||
|
||||
#region "Write exclusive"
|
||||
public static int WriteByteExclusive(ulong address, byte value)
|
||||
public static void MarkRegionAsModified(ulong address, ulong size)
|
||||
{
|
||||
bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
|
||||
|
||||
if (success)
|
||||
{
|
||||
ref int valueRef = ref _context.Memory.GetRefNoChecks<int>(address);
|
||||
|
||||
int currentValue = valueRef;
|
||||
|
||||
byte expected = (byte)_context.ExclusiveValueLow;
|
||||
|
||||
int expected32 = (currentValue & ~byte.MaxValue) | expected;
|
||||
int desired32 = (currentValue & ~byte.MaxValue) | value;
|
||||
|
||||
success = Interlocked.CompareExchange(ref valueRef, desired32, expected32) == expected32;
|
||||
|
||||
if (success)
|
||||
{
|
||||
ClearExclusive();
|
||||
}
|
||||
}
|
||||
|
||||
return success ? 0 : 1;
|
||||
GetMemoryManager().MarkRegionAsModified(address, size);
|
||||
}
|
||||
|
||||
public static int WriteUInt16Exclusive(ulong address, ushort value)
|
||||
public static void ThrowInvalidMemoryAccess(ulong address)
|
||||
{
|
||||
bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
|
||||
|
||||
if (success)
|
||||
{
|
||||
ref int valueRef = ref _context.Memory.GetRefNoChecks<int>(address);
|
||||
|
||||
int currentValue = valueRef;
|
||||
|
||||
ushort expected = (ushort)_context.ExclusiveValueLow;
|
||||
|
||||
int expected32 = (currentValue & ~ushort.MaxValue) | expected;
|
||||
int desired32 = (currentValue & ~ushort.MaxValue) | value;
|
||||
|
||||
success = Interlocked.CompareExchange(ref valueRef, desired32, expected32) == expected32;
|
||||
|
||||
if (success)
|
||||
{
|
||||
ClearExclusive();
|
||||
}
|
||||
}
|
||||
|
||||
return success ? 0 : 1;
|
||||
}
|
||||
|
||||
public static int WriteUInt32Exclusive(ulong address, uint value)
|
||||
{
|
||||
bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
|
||||
|
||||
if (success)
|
||||
{
|
||||
ref int valueRef = ref _context.Memory.GetRef<int>(address);
|
||||
|
||||
success = Interlocked.CompareExchange(ref valueRef, (int)value, (int)_context.ExclusiveValueLow) == (int)_context.ExclusiveValueLow;
|
||||
|
||||
if (success)
|
||||
{
|
||||
ClearExclusive();
|
||||
}
|
||||
}
|
||||
|
||||
return success ? 0 : 1;
|
||||
}
|
||||
|
||||
public static int WriteUInt64Exclusive(ulong address, ulong value)
|
||||
{
|
||||
bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
|
||||
|
||||
if (success)
|
||||
{
|
||||
ref long valueRef = ref _context.Memory.GetRef<long>(address);
|
||||
|
||||
success = Interlocked.CompareExchange(ref valueRef, (long)value, (long)_context.ExclusiveValueLow) == (long)_context.ExclusiveValueLow;
|
||||
|
||||
if (success)
|
||||
{
|
||||
ClearExclusive();
|
||||
}
|
||||
}
|
||||
|
||||
return success ? 0 : 1;
|
||||
}
|
||||
|
||||
public static int WriteVector128Exclusive(ulong address, V128 value)
|
||||
{
|
||||
bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
|
||||
|
||||
if (success)
|
||||
{
|
||||
V128 expected = new V128(_context.ExclusiveValueLow, _context.ExclusiveValueHigh);
|
||||
|
||||
ref V128 location = ref _context.Memory.GetRef<V128>(address);
|
||||
|
||||
success = MemoryManagerPal.CompareAndSwap128(ref location, expected, value) == expected;
|
||||
|
||||
if (success)
|
||||
{
|
||||
ClearExclusive();
|
||||
}
|
||||
}
|
||||
|
||||
return success ? 0 : 1;
|
||||
}
|
||||
#endregion
|
||||
|
||||
private static ulong GetMaskedExclusiveAddress(ulong address)
|
||||
{
|
||||
return address & ~((4UL << ErgSizeLog2) - 1);
|
||||
throw new InvalidAccessException(address);
|
||||
}
|
||||
|
||||
public static ulong GetFunctionAddress(ulong address)
|
||||
|
|
@ -426,11 +252,6 @@ namespace ARMeilleure.Instructions
|
|||
return ptr;
|
||||
}
|
||||
|
||||
public static void ClearExclusive()
|
||||
{
|
||||
_context.ExclusiveAddress = ulong.MaxValue;
|
||||
}
|
||||
|
||||
public static bool CheckSynchronization()
|
||||
{
|
||||
Statistics.PauseTimer();
|
||||
|
|
@ -444,7 +265,7 @@ namespace ARMeilleure.Instructions
|
|||
return context.Running;
|
||||
}
|
||||
|
||||
public static State.ExecutionContext GetContext()
|
||||
public static ExecutionContext GetContext()
|
||||
{
|
||||
return _context.Context;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue