Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan
emmauss
parent
1ba58e9942
commit
a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
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@ -2,7 +2,7 @@
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<PropertyGroup>
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<TargetFramework>netcoreapp2.1</TargetFramework>
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<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
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<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
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<Configurations>Debug;Release;Profile Debug;Profile Release</Configurations>
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</PropertyGroup>
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@ -33,6 +33,7 @@
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<ItemGroup>
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<ProjectReference Include="..\Ryujinx.Profiler\Ryujinx.Profiler.csproj" />
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<ProjectReference Include="..\ARMeilleure\ARMeilleure.csproj" />
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</ItemGroup>
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</Project>
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@ -1,66 +0,0 @@
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Threading;
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namespace ChocolArm64
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{
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public class CpuThread
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{
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public CpuThreadState ThreadState { get; private set; }
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public MemoryManager Memory { get; private set; }
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private Translator _translator;
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public Thread Work;
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public event EventHandler WorkFinished;
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private int _isExecuting;
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public CpuThread(Translator translator, MemoryManager memory, long entrypoint)
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{
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_translator = translator;
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Memory = memory;
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ThreadState = new CpuThreadState();
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ThreadState.Running = true;
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Work = new Thread(delegate()
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{
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translator.ExecuteSubroutine(this, entrypoint);
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WorkFinished?.Invoke(this, EventArgs.Empty);
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});
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}
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public bool Execute()
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{
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if (Interlocked.Exchange(ref _isExecuting, 1) == 1)
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{
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return false;
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}
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Work.Start();
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return true;
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}
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public void StopExecution()
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{
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ThreadState.Running = false;
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}
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public void RequestInterrupt()
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{
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ThreadState.RequestInterrupt();
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}
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public bool IsCurrentThread()
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{
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return Thread.CurrentThread == Work;
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}
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}
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}
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@ -462,11 +462,11 @@ namespace ChocolArm64.Instructions
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switch (size)
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{
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case 0: fallbackMethodName = nameof(MemoryManager.WriteVector8); break;
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case 1: fallbackMethodName = nameof(MemoryManager.WriteVector16); break;
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case 2: fallbackMethodName = nameof(MemoryManager.WriteVector32); break;
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case 3: fallbackMethodName = nameof(MemoryManager.WriteVector64); break;
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case 4: fallbackMethodName = nameof(MemoryManager.WriteVector128); break;
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case 0: fallbackMethodName = nameof(MemoryManager.WriteVector8); break;
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case 1: fallbackMethodName = nameof(MemoryManager.WriteVector16); break;
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case 2: fallbackMethodName = nameof(MemoryManager.WriteVector32); break;
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case 3: fallbackMethodName = nameof(MemoryManager.WriteVector64); break;
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case 4: fallbackMethodName = nameof(MemoryManager.WriteVector128Internal); break;
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}
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context.EmitCall(typeof(MemoryManager), fallbackMethodName);
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@ -31,8 +31,8 @@ namespace ChocolArm64.Instructions
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{
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case 0b11_011_0000_0000_001: propName = nameof(CpuThreadState.CtrEl0); break;
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case 0b11_011_0000_0000_111: propName = nameof(CpuThreadState.DczidEl0); break;
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case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.Fpcr); break;
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case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.Fpsr); break;
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case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.CFpcr); break;
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case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.CFpsr); break;
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case 0b11_011_1101_0000_010: propName = nameof(CpuThreadState.TpidrEl0); break;
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case 0b11_011_1101_0000_011: propName = nameof(CpuThreadState.Tpidr); break;
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case 0b11_011_1110_0000_000: propName = nameof(CpuThreadState.CntfrqEl0); break;
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@ -65,8 +65,8 @@ namespace ChocolArm64.Instructions
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switch (GetPackedId(op))
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{
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case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.Fpcr); break;
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case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.Fpsr); break;
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case 0b11_011_0100_0100_000: propName = nameof(CpuThreadState.CFpcr); break;
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case 0b11_011_0100_0100_001: propName = nameof(CpuThreadState.CFpsr); break;
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case 0b11_011_1101_0000_010: propName = nameof(CpuThreadState.TpidrEl0); break;
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default: throw new NotImplementedException($"Unknown MSR at {op.Position:x16}");
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@ -82,7 +82,7 @@ namespace ChocolArm64.Instructions
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{
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public static float FPConvert(ushort valueBits, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat16_32.FPConvert: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat16_32.FPConvert: state.Fpcr = 0x{state.CFpcr:X8}");
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double real = valueBits.FPUnpackCv(out FpType type, out bool sign, state);
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@ -322,13 +322,13 @@ namespace ChocolArm64.Instructions
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{
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int enable = (int)exc + 8;
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if ((state.Fpcr & (1 << enable)) != 0)
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if ((state.CFpcr & (1 << enable)) != 0)
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{
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throw new NotImplementedException("Floating-point trap handling.");
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}
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else
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{
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state.Fpsr |= 1 << (int)exc;
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state.CFpsr |= 1 << (int)exc;
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}
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}
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}
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@ -337,7 +337,7 @@ namespace ChocolArm64.Instructions
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{
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public static ushort FPConvert(float value, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32_16.FPConvert: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32_16.FPConvert: state.Fpcr = 0x{state.CFpcr:X8}");
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double real = value.FPUnpackCv(out FpType type, out bool sign, out uint valueBits, state);
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@ -609,13 +609,13 @@ namespace ChocolArm64.Instructions
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{
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int enable = (int)exc + 8;
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if ((state.Fpcr & (1 << enable)) != 0)
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if ((state.CFpcr & (1 << enable)) != 0)
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{
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throw new NotImplementedException("Floating-point trap handling.");
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}
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else
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{
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state.Fpsr |= 1 << (int)exc;
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state.CFpsr |= 1 << (int)exc;
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}
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}
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}
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@ -624,7 +624,7 @@ namespace ChocolArm64.Instructions
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{
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public static float FPAdd(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPAdd: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPAdd: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
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value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
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@ -672,7 +672,7 @@ namespace ChocolArm64.Instructions
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public static int FPCompare(float value1, float value2, bool signalNaNs, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompare: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
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value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
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@ -709,7 +709,7 @@ namespace ChocolArm64.Instructions
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public static float FPCompareEQ(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareEQ: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareEQ: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
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value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
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@ -735,7 +735,7 @@ namespace ChocolArm64.Instructions
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public static float FPCompareGE(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareGE: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareGE: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
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value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
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@ -758,7 +758,7 @@ namespace ChocolArm64.Instructions
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public static float FPCompareGT(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareGT: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareGT: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
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value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
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@ -782,7 +782,7 @@ namespace ChocolArm64.Instructions
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static float FPCompareLE(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareLE: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareLE: state.Fpcr = 0x{state.CFpcr:X8}");
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return FPCompareGE(value2, value1, state);
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}
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@ -790,14 +790,14 @@ namespace ChocolArm64.Instructions
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static float FPCompareLT(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompareLT: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPCompareLT: state.Fpcr = 0x{state.CFpcr:X8}");
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return FPCompareGT(value2, value1, state);
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}
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public static float FPDiv(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPDiv: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
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value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
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@ -846,7 +846,7 @@ namespace ChocolArm64.Instructions
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public static float FPMax(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMax: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMax: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
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value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
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@ -899,7 +899,7 @@ namespace ChocolArm64.Instructions
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public static float FPMaxNum(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMaxNum: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMaxNum: state.Fpcr = 0x{state.CFpcr:X8}");
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value1.FPUnpack(out FpType type1, out _, out _, state);
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value2.FPUnpack(out FpType type2, out _, out _, state);
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@ -918,7 +918,7 @@ namespace ChocolArm64.Instructions
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public static float FPMin(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMin: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMin: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
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value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
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@ -971,7 +971,7 @@ namespace ChocolArm64.Instructions
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public static float FPMinNum(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMinNum: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMinNum: state.Fpcr = 0x{state.CFpcr:X8}");
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value1.FPUnpack(out FpType type1, out _, out _, state);
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value2.FPUnpack(out FpType type2, out _, out _, state);
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@ -990,7 +990,7 @@ namespace ChocolArm64.Instructions
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public static float FPMul(float value1, float value2, CpuThreadState state)
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{
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMul: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMul: state.Fpcr = 0x{state.CFpcr:X8}");
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
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value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
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@ -1038,7 +1038,7 @@ namespace ChocolArm64.Instructions
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float value2,
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CpuThreadState state)
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{
|
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Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMulAdd: state.Fpcr = 0x{state.Fpcr:X8}");
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMulAdd: state.Fpcr = 0x{state.CFpcr:X8}");
|
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|
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valueA = valueA.FPUnpack(out FpType typeA, out bool signA, out uint addend, state);
|
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value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
|
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@ -1108,7 +1108,7 @@ namespace ChocolArm64.Instructions
|
|||
float value2,
|
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CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMulSub: state.Fpcr = 0x{state.Fpcr:X8}");
|
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Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMulSub: state.Fpcr = 0x{state.CFpcr:X8}");
|
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|
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value1 = value1.FPNeg();
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|
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@ -1117,7 +1117,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPMulX(float value1, float value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPMulX: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPMulX: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
|
||||
|
|
@ -1159,7 +1159,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPRecipEstimate(float value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRecipEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRecipEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value.FPUnpack(out FpType type, out bool sign, out uint op, state);
|
||||
|
||||
|
|
@ -1248,7 +1248,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPRecipStepFused(float value1, float value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRecipStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRecipStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPNeg();
|
||||
|
||||
|
|
@ -1291,7 +1291,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPRecpX(float value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRecpX: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRecpX: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value.FPUnpack(out FpType type, out bool sign, out uint op, state);
|
||||
|
||||
|
|
@ -1315,7 +1315,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPRSqrtEstimate(float value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRSqrtEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRSqrtEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value.FPUnpack(out FpType type, out bool sign, out uint op, state);
|
||||
|
||||
|
|
@ -1380,7 +1380,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPRSqrtStepFused(float value1, float value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPRSqrtStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPRSqrtStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPNeg();
|
||||
|
||||
|
|
@ -1423,7 +1423,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPSqrt(float value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPSqrt: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPSqrt: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value = value.FPUnpack(out FpType type, out bool sign, out uint op, state);
|
||||
|
||||
|
|
@ -1464,7 +1464,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static float FPSub(float value1, float value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPSub: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat32.FPSub: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2, state);
|
||||
|
|
@ -1693,13 +1693,13 @@ namespace ChocolArm64.Instructions
|
|||
{
|
||||
int enable = (int)exc + 8;
|
||||
|
||||
if ((state.Fpcr & (1 << enable)) != 0)
|
||||
if ((state.CFpcr & (1 << enable)) != 0)
|
||||
{
|
||||
throw new NotImplementedException("Floating-point trap handling.");
|
||||
}
|
||||
else
|
||||
{
|
||||
state.Fpsr |= 1 << (int)exc;
|
||||
state.CFpsr |= 1 << (int)exc;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1708,7 +1708,7 @@ namespace ChocolArm64.Instructions
|
|||
{
|
||||
public static double FPAdd(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPAdd: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPAdd: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -1756,7 +1756,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static int FPCompare(double value1, double value2, bool signalNaNs, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompare: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
|
||||
|
|
@ -1793,7 +1793,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPCompareEQ(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareEQ: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareEQ: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
|
||||
|
|
@ -1819,7 +1819,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPCompareGE(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareGE: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareGE: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
|
||||
|
|
@ -1842,7 +1842,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPCompareGT(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareGT: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareGT: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out _, out _, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out _, out _, state);
|
||||
|
|
@ -1866,7 +1866,7 @@ namespace ChocolArm64.Instructions
|
|||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
public static double FPCompareLE(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareLE: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareLE: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
return FPCompareGE(value2, value1, state);
|
||||
}
|
||||
|
|
@ -1874,14 +1874,14 @@ namespace ChocolArm64.Instructions
|
|||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
public static double FPCompareLT(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompareLT: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPCompareLT: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
return FPCompareGT(value2, value1, state);
|
||||
}
|
||||
|
||||
public static double FPDiv(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPDiv: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -1930,7 +1930,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPMax(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMax: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMax: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -1983,7 +1983,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPMaxNum(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMaxNum: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMaxNum: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1.FPUnpack(out FpType type1, out _, out _, state);
|
||||
value2.FPUnpack(out FpType type2, out _, out _, state);
|
||||
|
|
@ -2002,7 +2002,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPMin(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMin: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMin: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -2055,7 +2055,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPMinNum(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMinNum: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMinNum: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1.FPUnpack(out FpType type1, out _, out _, state);
|
||||
value2.FPUnpack(out FpType type2, out _, out _, state);
|
||||
|
|
@ -2074,7 +2074,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPMul(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMul: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMul: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -2122,7 +2122,7 @@ namespace ChocolArm64.Instructions
|
|||
double value2,
|
||||
CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMulAdd: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMulAdd: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
valueA = valueA.FPUnpack(out FpType typeA, out bool signA, out ulong addend, state);
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
|
|
@ -2192,7 +2192,7 @@ namespace ChocolArm64.Instructions
|
|||
double value2,
|
||||
CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMulSub: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMulSub: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPNeg();
|
||||
|
||||
|
|
@ -2201,7 +2201,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPMulX(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPMulX: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPMulX: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -2243,7 +2243,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPRecipEstimate(double value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRecipEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRecipEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
|
||||
|
||||
|
|
@ -2332,7 +2332,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPRecipStepFused(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRecipStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRecipStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPNeg();
|
||||
|
||||
|
|
@ -2375,7 +2375,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPRecpX(double value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRecpX: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRecpX: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
|
||||
|
||||
|
|
@ -2399,7 +2399,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPRSqrtEstimate(double value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRSqrtEstimate: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRSqrtEstimate: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
|
||||
|
||||
|
|
@ -2464,7 +2464,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPRSqrtStepFused(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPRSqrtStepFused: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPRSqrtStepFused: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPNeg();
|
||||
|
||||
|
|
@ -2507,7 +2507,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPSqrt(double value, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPSqrt: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPSqrt: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value = value.FPUnpack(out FpType type, out bool sign, out ulong op, state);
|
||||
|
||||
|
|
@ -2548,7 +2548,7 @@ namespace ChocolArm64.Instructions
|
|||
|
||||
public static double FPSub(double value1, double value2, CpuThreadState state)
|
||||
{
|
||||
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPSub: state.Fpcr = 0x{state.Fpcr:X8}");
|
||||
Debug.WriteLineIf(state.CFpcr != 0, $"SoftFloat64.FPSub: state.Fpcr = 0x{state.CFpcr:X8}");
|
||||
|
||||
value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1, state);
|
||||
value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2, state);
|
||||
|
|
@ -2777,13 +2777,13 @@ namespace ChocolArm64.Instructions
|
|||
{
|
||||
int enable = (int)exc + 8;
|
||||
|
||||
if ((state.Fpcr & (1 << enable)) != 0)
|
||||
if ((state.CFpcr & (1 << enable)) != 0)
|
||||
{
|
||||
throw new NotImplementedException("Floating-point trap handling.");
|
||||
}
|
||||
else
|
||||
{
|
||||
state.Fpsr |= 1 << (int)exc;
|
||||
state.CFpsr |= 1 << (int)exc;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ using static ChocolArm64.Memory.MemoryManagement;
|
|||
|
||||
namespace ChocolArm64.Memory
|
||||
{
|
||||
public unsafe class MemoryManager : IMemory, IDisposable
|
||||
public unsafe class MemoryManager : ARMeilleure.Memory.IMemoryManager
|
||||
{
|
||||
public const int PageBits = 12;
|
||||
public const int PageSize = 1 << PageBits;
|
||||
|
|
@ -880,7 +880,7 @@ namespace ChocolArm64.Memory
|
|||
}
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
public void WriteVector128(long position, Vector128<float> value)
|
||||
public void WriteVector128Internal(long position, Vector128<float> value)
|
||||
{
|
||||
if (Sse.IsSupported && (position & 15) == 0)
|
||||
{
|
||||
|
|
@ -893,6 +893,12 @@ namespace ChocolArm64.Memory
|
|||
}
|
||||
}
|
||||
|
||||
public void WriteVector128(long position, ARMeilleure.State.V128 value)
|
||||
{
|
||||
WriteUInt64(position + 0, value.GetUInt64(0));
|
||||
WriteUInt64(position + 8, value.GetUInt64(1));
|
||||
}
|
||||
|
||||
public void WriteBytes(long position, byte[] data)
|
||||
{
|
||||
long endAddr = position + data.Length;
|
||||
|
|
|
|||
|
|
@ -1,24 +1,27 @@
|
|||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
public static class Optimizations
|
||||
namespace ChocolArm64
|
||||
{
|
||||
public static bool AssumeStrictAbiCompliance { get; set; }
|
||||
public static class Optimizations
|
||||
{
|
||||
public static bool AssumeStrictAbiCompliance { get; set; } = true;
|
||||
|
||||
public static bool FastFP { get; set; } = true;
|
||||
public static bool FastFP { get; set; } = true;
|
||||
|
||||
private const bool UseAllSseIfAvailable = true;
|
||||
private const bool UseAllSseIfAvailable = true;
|
||||
|
||||
public static bool UseSseIfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse2IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse3IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSsse3IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse41IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse42IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSseIfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse2IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse3IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSsse3IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse41IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
public static bool UseSse42IfAvailable { get; set; } = UseAllSseIfAvailable;
|
||||
|
||||
internal static bool UseSse => UseSseIfAvailable && Sse.IsSupported;
|
||||
internal static bool UseSse2 => UseSse2IfAvailable && Sse2.IsSupported;
|
||||
internal static bool UseSse3 => UseSse3IfAvailable && Sse3.IsSupported;
|
||||
internal static bool UseSsse3 => UseSsse3IfAvailable && Ssse3.IsSupported;
|
||||
internal static bool UseSse41 => UseSse41IfAvailable && Sse41.IsSupported;
|
||||
internal static bool UseSse42 => UseSse42IfAvailable && Sse42.IsSupported;
|
||||
internal static bool UseSse => UseSseIfAvailable && Sse.IsSupported;
|
||||
internal static bool UseSse2 => UseSse2IfAvailable && Sse2.IsSupported;
|
||||
internal static bool UseSse3 => UseSse3IfAvailable && Sse3.IsSupported;
|
||||
internal static bool UseSsse3 => UseSsse3IfAvailable && Ssse3.IsSupported;
|
||||
internal static bool UseSse41 => UseSse41IfAvailable && Sse41.IsSupported;
|
||||
internal static bool UseSse42 => UseSse42IfAvailable && Sse42.IsSupported;
|
||||
}
|
||||
}
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
using ChocolArm64.Events;
|
||||
using ChocolArm64.Translation;
|
||||
using System;
|
||||
using System.Diagnostics;
|
||||
using System.Runtime.CompilerServices;
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
using static ChocolArm64.Instructions.VectorHelper;
|
||||
|
||||
namespace ChocolArm64.State
|
||||
{
|
||||
public class CpuThreadState
|
||||
public class CpuThreadState : ARMeilleure.State.IExecutionContext
|
||||
{
|
||||
private const int MinCountForCheck = 40000;
|
||||
|
||||
|
|
@ -24,7 +25,7 @@ namespace ChocolArm64.State
|
|||
V16, V17, V18, V19, V20, V21, V22, V23,
|
||||
V24, V25, V26, V27, V28, V29, V30, V31;
|
||||
|
||||
public bool Aarch32;
|
||||
public bool IsAarch32 { get; set; }
|
||||
|
||||
public bool Thumb;
|
||||
public bool BigEndian;
|
||||
|
|
@ -45,8 +46,20 @@ namespace ChocolArm64.State
|
|||
public long TpidrEl0 { get; set; }
|
||||
public long Tpidr { get; set; }
|
||||
|
||||
public int Fpcr { get; set; }
|
||||
public int Fpsr { get; set; }
|
||||
public int CFpcr { get; set; }
|
||||
public int CFpsr { get; set; }
|
||||
|
||||
public ARMeilleure.State.FPCR Fpcr
|
||||
{
|
||||
get => (ARMeilleure.State.FPCR)CFpcr;
|
||||
set => CFpcr = (int)value;
|
||||
}
|
||||
|
||||
public ARMeilleure.State.FPSR Fpsr
|
||||
{
|
||||
get => (ARMeilleure.State.FPSR)CFpsr;
|
||||
set => CFpsr = (int)value;
|
||||
}
|
||||
|
||||
public int Psr
|
||||
{
|
||||
|
|
@ -73,10 +86,10 @@ namespace ChocolArm64.State
|
|||
}
|
||||
}
|
||||
|
||||
public event EventHandler<EventArgs> Interrupt;
|
||||
public event EventHandler<InstExceptionEventArgs> Break;
|
||||
public event EventHandler<InstExceptionEventArgs> SvcCall;
|
||||
public event EventHandler<InstUndefinedEventArgs> Undefined;
|
||||
public event EventHandler<EventArgs> Interrupt;
|
||||
public event EventHandler<ARMeilleure.State.InstExceptionEventArgs> Break;
|
||||
public event EventHandler<ARMeilleure.State.InstExceptionEventArgs> SupervisorCall;
|
||||
public event EventHandler<ARMeilleure.State.InstUndefinedEventArgs> Undefined;
|
||||
|
||||
private static Stopwatch _tickCounter;
|
||||
|
||||
|
|
@ -92,6 +105,8 @@ namespace ChocolArm64.State
|
|||
public CpuThreadState()
|
||||
{
|
||||
ClearExclusiveAddress();
|
||||
|
||||
Running = true;
|
||||
}
|
||||
|
||||
static CpuThreadState()
|
||||
|
|
@ -151,29 +166,165 @@ namespace ChocolArm64.State
|
|||
}
|
||||
}
|
||||
|
||||
internal void RequestInterrupt()
|
||||
public ulong GetX(int index)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0: return X0;
|
||||
case 1: return X1;
|
||||
case 2: return X2;
|
||||
case 3: return X3;
|
||||
case 4: return X4;
|
||||
case 5: return X5;
|
||||
case 6: return X6;
|
||||
case 7: return X7;
|
||||
case 8: return X8;
|
||||
case 9: return X9;
|
||||
case 10: return X10;
|
||||
case 11: return X11;
|
||||
case 12: return X12;
|
||||
case 13: return X13;
|
||||
case 14: return X14;
|
||||
case 15: return X15;
|
||||
case 16: return X16;
|
||||
case 17: return X17;
|
||||
case 18: return X18;
|
||||
case 19: return X19;
|
||||
case 20: return X20;
|
||||
case 21: return X21;
|
||||
case 22: return X22;
|
||||
case 23: return X23;
|
||||
case 24: return X24;
|
||||
case 25: return X25;
|
||||
case 26: return X26;
|
||||
case 27: return X27;
|
||||
case 28: return X28;
|
||||
case 29: return X29;
|
||||
case 30: return X30;
|
||||
case 31: return X31;
|
||||
|
||||
default: throw new ArgumentOutOfRangeException(nameof(index));
|
||||
}
|
||||
}
|
||||
|
||||
public void SetX(int index, ulong value)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0: X0 = value; break;
|
||||
case 1: X1 = value; break;
|
||||
case 2: X2 = value; break;
|
||||
case 3: X3 = value; break;
|
||||
case 4: X4 = value; break;
|
||||
case 5: X5 = value; break;
|
||||
case 6: X6 = value; break;
|
||||
case 7: X7 = value; break;
|
||||
case 8: X8 = value; break;
|
||||
case 9: X9 = value; break;
|
||||
case 10: X10 = value; break;
|
||||
case 11: X11 = value; break;
|
||||
case 12: X12 = value; break;
|
||||
case 13: X13 = value; break;
|
||||
case 14: X14 = value; break;
|
||||
case 15: X15 = value; break;
|
||||
case 16: X16 = value; break;
|
||||
case 17: X17 = value; break;
|
||||
case 18: X18 = value; break;
|
||||
case 19: X19 = value; break;
|
||||
case 20: X20 = value; break;
|
||||
case 21: X21 = value; break;
|
||||
case 22: X22 = value; break;
|
||||
case 23: X23 = value; break;
|
||||
case 24: X24 = value; break;
|
||||
case 25: X25 = value; break;
|
||||
case 26: X26 = value; break;
|
||||
case 27: X27 = value; break;
|
||||
case 28: X28 = value; break;
|
||||
case 29: X29 = value; break;
|
||||
case 30: X30 = value; break;
|
||||
case 31: X31 = value; break;
|
||||
|
||||
default: throw new ArgumentOutOfRangeException(nameof(index));
|
||||
}
|
||||
}
|
||||
|
||||
public ARMeilleure.State.V128 GetV(int index)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0: return new ARMeilleure.State.V128(VectorExtractIntZx(V0, 0, 3), VectorExtractIntZx(V0, 1, 3));
|
||||
case 1: return new ARMeilleure.State.V128(VectorExtractIntZx(V1, 0, 3), VectorExtractIntZx(V1, 1, 3));
|
||||
case 2: return new ARMeilleure.State.V128(VectorExtractIntZx(V2, 0, 3), VectorExtractIntZx(V2, 1, 3));
|
||||
case 3: return new ARMeilleure.State.V128(VectorExtractIntZx(V3, 0, 3), VectorExtractIntZx(V3, 1, 3));
|
||||
case 4: return new ARMeilleure.State.V128(VectorExtractIntZx(V4, 0, 3), VectorExtractIntZx(V4, 1, 3));
|
||||
case 5: return new ARMeilleure.State.V128(VectorExtractIntZx(V5, 0, 3), VectorExtractIntZx(V5, 1, 3));
|
||||
case 6: return new ARMeilleure.State.V128(VectorExtractIntZx(V6, 0, 3), VectorExtractIntZx(V6, 1, 3));
|
||||
case 7: return new ARMeilleure.State.V128(VectorExtractIntZx(V7, 0, 3), VectorExtractIntZx(V7, 1, 3));
|
||||
case 8: return new ARMeilleure.State.V128(VectorExtractIntZx(V8, 0, 3), VectorExtractIntZx(V8, 1, 3));
|
||||
case 9: return new ARMeilleure.State.V128(VectorExtractIntZx(V9, 0, 3), VectorExtractIntZx(V9, 1, 3));
|
||||
case 10: return new ARMeilleure.State.V128(VectorExtractIntZx(V10, 0, 3), VectorExtractIntZx(V10, 1, 3));
|
||||
case 11: return new ARMeilleure.State.V128(VectorExtractIntZx(V11, 0, 3), VectorExtractIntZx(V11, 1, 3));
|
||||
case 12: return new ARMeilleure.State.V128(VectorExtractIntZx(V12, 0, 3), VectorExtractIntZx(V12, 1, 3));
|
||||
case 13: return new ARMeilleure.State.V128(VectorExtractIntZx(V13, 0, 3), VectorExtractIntZx(V13, 1, 3));
|
||||
case 14: return new ARMeilleure.State.V128(VectorExtractIntZx(V14, 0, 3), VectorExtractIntZx(V14, 1, 3));
|
||||
case 15: return new ARMeilleure.State.V128(VectorExtractIntZx(V15, 0, 3), VectorExtractIntZx(V15, 1, 3));
|
||||
case 16: return new ARMeilleure.State.V128(VectorExtractIntZx(V16, 0, 3), VectorExtractIntZx(V16, 1, 3));
|
||||
case 17: return new ARMeilleure.State.V128(VectorExtractIntZx(V17, 0, 3), VectorExtractIntZx(V17, 1, 3));
|
||||
case 18: return new ARMeilleure.State.V128(VectorExtractIntZx(V18, 0, 3), VectorExtractIntZx(V18, 1, 3));
|
||||
case 19: return new ARMeilleure.State.V128(VectorExtractIntZx(V19, 0, 3), VectorExtractIntZx(V19, 1, 3));
|
||||
case 20: return new ARMeilleure.State.V128(VectorExtractIntZx(V20, 0, 3), VectorExtractIntZx(V20, 1, 3));
|
||||
case 21: return new ARMeilleure.State.V128(VectorExtractIntZx(V21, 0, 3), VectorExtractIntZx(V21, 1, 3));
|
||||
case 22: return new ARMeilleure.State.V128(VectorExtractIntZx(V22, 0, 3), VectorExtractIntZx(V22, 1, 3));
|
||||
case 23: return new ARMeilleure.State.V128(VectorExtractIntZx(V23, 0, 3), VectorExtractIntZx(V23, 1, 3));
|
||||
case 24: return new ARMeilleure.State.V128(VectorExtractIntZx(V24, 0, 3), VectorExtractIntZx(V24, 1, 3));
|
||||
case 25: return new ARMeilleure.State.V128(VectorExtractIntZx(V25, 0, 3), VectorExtractIntZx(V25, 1, 3));
|
||||
case 26: return new ARMeilleure.State.V128(VectorExtractIntZx(V26, 0, 3), VectorExtractIntZx(V26, 1, 3));
|
||||
case 27: return new ARMeilleure.State.V128(VectorExtractIntZx(V27, 0, 3), VectorExtractIntZx(V27, 1, 3));
|
||||
case 28: return new ARMeilleure.State.V128(VectorExtractIntZx(V28, 0, 3), VectorExtractIntZx(V28, 1, 3));
|
||||
case 29: return new ARMeilleure.State.V128(VectorExtractIntZx(V29, 0, 3), VectorExtractIntZx(V29, 1, 3));
|
||||
case 30: return new ARMeilleure.State.V128(VectorExtractIntZx(V30, 0, 3), VectorExtractIntZx(V30, 1, 3));
|
||||
case 31: return new ARMeilleure.State.V128(VectorExtractIntZx(V31, 0, 3), VectorExtractIntZx(V31, 1, 3));
|
||||
|
||||
default: throw new ArgumentOutOfRangeException(nameof(index));
|
||||
}
|
||||
}
|
||||
|
||||
public bool GetPstateFlag(ARMeilleure.State.PState flag)
|
||||
{
|
||||
switch (flag)
|
||||
{
|
||||
case ARMeilleure.State.PState.NFlag: return Negative;
|
||||
case ARMeilleure.State.PState.ZFlag: return Zero;
|
||||
case ARMeilleure.State.PState.CFlag: return Carry;
|
||||
case ARMeilleure.State.PState.VFlag: return Overflow;
|
||||
|
||||
default: throw new ArgumentOutOfRangeException(nameof(flag));
|
||||
}
|
||||
}
|
||||
|
||||
public void RequestInterrupt()
|
||||
{
|
||||
_interrupted = true;
|
||||
}
|
||||
|
||||
internal void OnBreak(long position, int imm)
|
||||
{
|
||||
Break?.Invoke(this, new InstExceptionEventArgs(position, imm));
|
||||
Break?.Invoke(this, new ARMeilleure.State.InstExceptionEventArgs((ulong)position, imm));
|
||||
}
|
||||
|
||||
internal void OnSvcCall(long position, int imm)
|
||||
{
|
||||
SvcCall?.Invoke(this, new InstExceptionEventArgs(position, imm));
|
||||
SupervisorCall?.Invoke(this, new ARMeilleure.State.InstExceptionEventArgs((ulong)position, imm));
|
||||
}
|
||||
|
||||
internal void OnUndefined(long position, int rawOpCode)
|
||||
{
|
||||
Undefined?.Invoke(this, new InstUndefinedEventArgs(position, rawOpCode));
|
||||
Undefined?.Invoke(this, new ARMeilleure.State.InstUndefinedEventArgs((ulong)position, rawOpCode));
|
||||
}
|
||||
|
||||
internal ExecutionMode GetExecutionMode()
|
||||
{
|
||||
if (!Aarch32)
|
||||
if (!IsAarch32)
|
||||
{
|
||||
return ExecutionMode.Aarch64;
|
||||
}
|
||||
|
|
@ -185,17 +336,19 @@ namespace ChocolArm64.State
|
|||
|
||||
internal bool GetFpcrFlag(Fpcr flag)
|
||||
{
|
||||
return (Fpcr & (1 << (int)flag)) != 0;
|
||||
return (CFpcr & (1 << (int)flag)) != 0;
|
||||
}
|
||||
|
||||
internal void SetFpsrFlag(Fpsr flag)
|
||||
{
|
||||
Fpsr |= 1 << (int)flag;
|
||||
CFpsr |= 1 << (int)flag;
|
||||
}
|
||||
|
||||
internal RoundMode FPRoundingMode()
|
||||
{
|
||||
return (RoundMode)((Fpcr >> (int)State.Fpcr.RMode) & 3);
|
||||
return (RoundMode)((CFpcr >> (int)State.Fpcr.RMode) & 3);
|
||||
}
|
||||
|
||||
public void Dispose() { }
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ using System.Threading;
|
|||
|
||||
namespace ChocolArm64.Translation
|
||||
{
|
||||
public class Translator
|
||||
public class Translator : ARMeilleure.Translation.ITranslator
|
||||
{
|
||||
private MemoryManager _memory;
|
||||
|
||||
|
|
@ -38,24 +38,18 @@ namespace ChocolArm64.Translation
|
|||
_queue = new TranslatorQueue();
|
||||
}
|
||||
|
||||
internal void ExecuteSubroutine(CpuThread thread, long position)
|
||||
public void Execute(ARMeilleure.State.IExecutionContext ctx, ulong address)
|
||||
{
|
||||
CpuThreadState state = (CpuThreadState)ctx;
|
||||
|
||||
long position = (long)address;
|
||||
|
||||
if (Interlocked.Increment(ref _threadCount) == 1)
|
||||
{
|
||||
_backgroundTranslator = new Thread(TranslateQueuedSubs);
|
||||
_backgroundTranslator.Start();
|
||||
}
|
||||
|
||||
ExecuteSubroutine(thread.ThreadState, position);
|
||||
|
||||
if (Interlocked.Decrement(ref _threadCount) == 0)
|
||||
{
|
||||
_queue.ForceSignal();
|
||||
}
|
||||
}
|
||||
|
||||
private void ExecuteSubroutine(CpuThreadState state, long position)
|
||||
{
|
||||
state.CurrentTranslator = this;
|
||||
|
||||
do
|
||||
|
|
@ -75,6 +69,11 @@ namespace ChocolArm64.Translation
|
|||
while (position != 0 && state.Running);
|
||||
|
||||
state.CurrentTranslator = null;
|
||||
|
||||
if (Interlocked.Decrement(ref _threadCount) == 0)
|
||||
{
|
||||
_queue.ForceSignal();
|
||||
}
|
||||
}
|
||||
|
||||
internal ArmSubroutine GetOrTranslateSubroutine(CpuThreadState state, long position, CallType cs)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue