Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
parent
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310 changed files with 37389 additions and 2086 deletions
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@ -21,7 +21,7 @@
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// Enable printing guest logs
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"logging_enable_guest": true,
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// Enable printing FS access logs. fs_global_access_log_mode must be 2 or 3
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"logging_enable_fs_access_log": false,
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@ -53,8 +53,8 @@
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// Sets the "GlobalAccessLogMode". Possible modes are 0-3
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"fs_global_access_log_mode": 0,
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// Enable or disable aggressive CPU optimizations
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"enable_aggressive_cpu_opts": true,
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// Use old ChocolArm64 ARM emulator
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"enable_legacy_jit": false,
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// Enable or disable ignoring missing services, this may cause instability
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"ignore_missing_services": false,
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@ -1,3 +1,4 @@
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using ARMeilleure;
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using LibHac.Fs;
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using OpenTK.Input;
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using Ryujinx.Common;
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@ -108,9 +109,9 @@ namespace Ryujinx
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public int FsGlobalAccessLogMode { get; private set; }
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/// <summary>
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/// Enable or Disable aggressive CPU optimizations
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/// Use old ChocolArm64 ARM emulator
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/// </summary>
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public bool EnableAggressiveCpuOpts { get; private set; }
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public bool EnableLegacyJit { get; private set; }
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/// <summary>
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/// Enable or disable ignoring missing services
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@ -239,10 +240,7 @@ namespace Ryujinx
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device.System.GlobalAccessLogMode = Instance.FsGlobalAccessLogMode;
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if (Instance.EnableAggressiveCpuOpts)
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{
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Optimizations.AssumeStrictAbiCompliance = true;
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}
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device.System.UseLegacyJit = Instance.EnableLegacyJit;
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ServiceConfiguration.IgnoreMissingServices = Instance.IgnoreMissingServices;
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@ -2,7 +2,7 @@
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<PropertyGroup>
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<TargetFramework>netcoreapp2.1</TargetFramework>
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<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
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<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
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<OutputType>Exe</OutputType>
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<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
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<Configurations>Debug;Release;Profile Debug;Profile Release</Configurations>
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@ -24,12 +24,12 @@
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</ItemGroup>
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<ItemGroup>
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<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
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<ProjectReference Include="..\Ryujinx.Audio\Ryujinx.Audio.csproj" />
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<ProjectReference Include="..\Ryujinx.Common\Ryujinx.Common.csproj" />
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<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
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<ProjectReference Include="..\Ryujinx.HLE\Ryujinx.HLE.csproj" />
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<ProjectReference Include="..\Ryujinx.Profiler\Ryujinx.Profiler.csproj" />
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<ProjectReference Include="..\ARMeilleure\ARMeilleure.csproj" />
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</ItemGroup>
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<ItemGroup>
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@ -20,7 +20,7 @@
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"enable_multicore_scheduling",
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"enable_fs_integrity_checks",
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"fs_global_access_log_mode",
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"enable_aggressive_cpu_opts",
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"enable_legacy_jit",
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"controller_type",
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"enable_keyboard",
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"keyboard_controls",
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"$id": "#/properties/fs_global_access_log_mode",
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"type": "integer",
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"title": "Enable FS access log",
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"description": "Enables FS access log output. Possible modes are 0-3. Modes 2 and 3 output to the console.",
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"description": "Enables FS access log output. Possible modes are 0-3. Modes 2 and 3 output to the console",
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"default": 0,
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"minimum": 0,
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"examples": [
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@ -472,12 +472,12 @@
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3
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]
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},
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"enable_aggressive_cpu_opts": {
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"$id": "#/properties/enable_aggressive_cpu_opts",
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"enable_legacy_jit": {
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"$id": "#/properties/enable_legacy_jit",
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"type": "boolean",
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"title": "Enable Aggressive CPU Optimizations",
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"description": "Enable or disable aggressive CPU optimizations",
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"default": true,
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"title": "Enable legacy JIT",
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"description": "Use old ChocolArm64 ARM emulator",
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"default": false,
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"examples": [
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true,
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false
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