Add a new JIT compiler for CPU code (#693)

* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan 2019-08-08 15:56:22 -03:00 committed by emmauss
parent 1ba58e9942
commit a731ab3a2a
310 changed files with 37389 additions and 2086 deletions

View file

@ -21,7 +21,7 @@
// Enable printing guest logs
"logging_enable_guest": true,
// Enable printing FS access logs. fs_global_access_log_mode must be 2 or 3
"logging_enable_fs_access_log": false,
@ -53,8 +53,8 @@
// Sets the "GlobalAccessLogMode". Possible modes are 0-3
"fs_global_access_log_mode": 0,
// Enable or disable aggressive CPU optimizations
"enable_aggressive_cpu_opts": true,
// Use old ChocolArm64 ARM emulator
"enable_legacy_jit": false,
// Enable or disable ignoring missing services, this may cause instability
"ignore_missing_services": false,

View file

@ -1,3 +1,4 @@
using ARMeilleure;
using LibHac.Fs;
using OpenTK.Input;
using Ryujinx.Common;
@ -108,9 +109,9 @@ namespace Ryujinx
public int FsGlobalAccessLogMode { get; private set; }
/// <summary>
/// Enable or Disable aggressive CPU optimizations
/// Use old ChocolArm64 ARM emulator
/// </summary>
public bool EnableAggressiveCpuOpts { get; private set; }
public bool EnableLegacyJit { get; private set; }
/// <summary>
/// Enable or disable ignoring missing services
@ -239,10 +240,7 @@ namespace Ryujinx
device.System.GlobalAccessLogMode = Instance.FsGlobalAccessLogMode;
if (Instance.EnableAggressiveCpuOpts)
{
Optimizations.AssumeStrictAbiCompliance = true;
}
device.System.UseLegacyJit = Instance.EnableLegacyJit;
ServiceConfiguration.IgnoreMissingServices = Instance.IgnoreMissingServices;

View file

@ -2,7 +2,7 @@
<PropertyGroup>
<TargetFramework>netcoreapp2.1</TargetFramework>
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
<RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
<OutputType>Exe</OutputType>
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
<Configurations>Debug;Release;Profile Debug;Profile Release</Configurations>
@ -24,12 +24,12 @@
</ItemGroup>
<ItemGroup>
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
<ProjectReference Include="..\Ryujinx.Audio\Ryujinx.Audio.csproj" />
<ProjectReference Include="..\Ryujinx.Common\Ryujinx.Common.csproj" />
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
<ProjectReference Include="..\Ryujinx.HLE\Ryujinx.HLE.csproj" />
<ProjectReference Include="..\Ryujinx.Profiler\Ryujinx.Profiler.csproj" />
<ProjectReference Include="..\ARMeilleure\ARMeilleure.csproj" />
</ItemGroup>
<ItemGroup>

View file

@ -20,7 +20,7 @@
"enable_multicore_scheduling",
"enable_fs_integrity_checks",
"fs_global_access_log_mode",
"enable_aggressive_cpu_opts",
"enable_legacy_jit",
"controller_type",
"enable_keyboard",
"keyboard_controls",
@ -462,7 +462,7 @@
"$id": "#/properties/fs_global_access_log_mode",
"type": "integer",
"title": "Enable FS access log",
"description": "Enables FS access log output. Possible modes are 0-3. Modes 2 and 3 output to the console.",
"description": "Enables FS access log output. Possible modes are 0-3. Modes 2 and 3 output to the console",
"default": 0,
"minimum": 0,
"examples": [
@ -472,12 +472,12 @@
3
]
},
"enable_aggressive_cpu_opts": {
"$id": "#/properties/enable_aggressive_cpu_opts",
"enable_legacy_jit": {
"$id": "#/properties/enable_legacy_jit",
"type": "boolean",
"title": "Enable Aggressive CPU Optimizations",
"description": "Enable or disable aggressive CPU optimizations",
"default": true,
"title": "Enable legacy JIT",
"description": "Use old ChocolArm64 ARM emulator",
"default": false,
"examples": [
true,
false