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Implement VORN (register) Arm32 instruction (#2396)

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gdkchan 2021-06-23 18:21:23 -03:00 • committed by GitHub
parent 49edf14a3e
commit ab9d4b862d
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4 changed files with 30 additions and 9 deletions
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1
ARMeilleure/Decoders/OpCodeTable.cs
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@ -907,6 +907,7 @@ namespace ARMeilleure.Decoders
SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, OpCode32SimdRegS.Create);
SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, OpCode32SimdRegS.Create);
SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, OpCode32SimdRegS.Create);
SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn, InstEmit32.Vorn_I, OpCode32SimdBinary.Create);
SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, OpCode32SimdBinary.Create);
SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, OpCode32SimdImm.Create);
SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, OpCode32SimdReg.Create);

18
ARMeilleure/Instructions/InstEmitSimdLogical32.cs
View file

@ -115,6 +115,24 @@ namespace ARMeilleure.Instructions
}
}
public static void Vorn_I(ArmEmitterContext context)
{
if (Optimizations.UseSse2)
{
Operand mask = context.VectorOne();
EmitVectorBinaryOpSimd32(context, (n, m) =>
{
m = context.AddIntrinsic(Intrinsic.X86Pandn, m, mask);
return context.AddIntrinsic(Intrinsic.X86Por, n, m);
});
}
else
{
EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, context.BitwiseNot(op2)));
}
}
public static void Vorr_I(ArmEmitterContext context)
{
if (Optimizations.UseSse2)

1
ARMeilleure/Instructions/InstName.cs
View file

@ -605,6 +605,7 @@ namespace ARMeilleure.Instructions
Vnmul,
Vnmla,
Vnmls,
Vorn,
Vorr,
Vpadd,
Vpmax,