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Misc cleanup (#708)

Browse source 
* Fix typos

* Remove unneeded using statements

* Enforce var style more

* Remove redundant qualifiers

* Fix some indentation

* Disable naming warnings on files with external enum names

* Fix build

* Mass find & replace for comments with no spacing

* Standardize todo capitalization and for/if spacing
This commit is contained in:
Alex Barney 2019-07-01 21:39:22 -05:00 • committed by Ac_K
parent 10c74182ba
commit b2b736abc2
205 changed files with 1020 additions and 1041 deletions
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2
ChocolArm64/Instructions/InstEmit32Helper.cs
View file

@ -24,7 +24,7 @@ namespace ChocolArm64.Instructions
}
else
{
context.EmitLdint(InstEmit32Helper.GetRegisterAlias(context.Mode, register));
context.EmitLdint(GetRegisterAlias(context.Mode, register));
}
}

14
ChocolArm64/Instructions/InstEmitAlu.cs
View file

@ -151,7 +151,7 @@ namespace ChocolArm64.Instructions
public static void Extr(ILEmitterCtx context)
{
//TODO: Ensure that the Shift is valid for the Is64Bits.
// TODO: Ensure that the Shift is valid for the Is64Bits.
OpCodeAluRs64 op = (OpCodeAluRs64)context.CurrOp;
context.EmitLdintzr(op.Rm);
@ -309,7 +309,7 @@ namespace ChocolArm64.Instructions
private static void EmitDiv(ILEmitterCtx context, OpCode ilOp)
{
//If Rm == 0, Rd = 0 (division by zero).
// If Rm == 0, Rd = 0 (division by zero).
context.EmitLdc_I(0);
EmitAluLoadRm(context);
@ -323,7 +323,7 @@ namespace ChocolArm64.Instructions
if (ilOp == OpCodes.Div)
{
//If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
// If Rn == INT_MIN && Rm == -1, Rd = INT_MIN (overflow).
long intMin = 1L << (context.CurrOp.GetBitsCount() - 1);
context.EmitLdc_I(intMin);
@ -381,10 +381,10 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.And);
//Note: Only 32-bits shift values are valid, so when the value is 64-bits
//we need to cast it to a 32-bits integer. This is fine because we
//AND the value and only keep the lower 5 or 6 bits anyway -- it
//could very well fit on a byte.
// Note: Only 32-bits shift values are valid, so when the value is 64-bits
// we need to cast it to a 32-bits integer. This is fine because we
// AND the value and only keep the lower 5 or 6 bits anyway -- it
// could very well fit on a byte.
if (context.CurrOp.RegisterSize != RegisterSize.Int32)
{
context.Emit(OpCodes.Conv_I4);

2
ChocolArm64/Instructions/InstEmitAlu32.cs
View file

@ -87,7 +87,7 @@ namespace ChocolArm64.Instructions
{
if (op.SetFlags)
{
//TODO: Load SPSR etc.
// TODO: Load SPSR etc.
context.EmitLdflg((int)PState.TBit);

20
ChocolArm64/Instructions/InstEmitAluHelper.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64.Instructions
{
public static void EmitAdcsCCheck(ILEmitterCtx context)
{
//C = (Rd == Rn && CIn) || Rd < Rn
// C = (Rd == Rn && CIn) || Rd < Rn
context.EmitSttmp();
context.EmitLdtmp();
context.EmitLdtmp();
@ -35,7 +35,7 @@ namespace ChocolArm64.Instructions
public static void EmitAddsCCheck(ILEmitterCtx context)
{
//C = Rd < Rn
// C = Rd < Rn
context.Emit(OpCodes.Dup);
EmitAluLoadRn(context);
@ -47,7 +47,7 @@ namespace ChocolArm64.Instructions
public static void EmitAddsVCheck(ILEmitterCtx context)
{
//V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
// V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
context.Emit(OpCodes.Dup);
EmitAluLoadRn(context);
@ -69,7 +69,7 @@ namespace ChocolArm64.Instructions
public static void EmitSbcsCCheck(ILEmitterCtx context)
{
//C = (Rn == Rm && CIn) || Rn > Rm
// C = (Rn == Rm && CIn) || Rn > Rm
EmitAluLoadOpers(context);
context.Emit(OpCodes.Ceq);
@ -88,7 +88,7 @@ namespace ChocolArm64.Instructions
public static void EmitSubsCCheck(ILEmitterCtx context)
{
//C = Rn == Rm || Rn > Rm = !(Rn < Rm)
// C = Rn == Rm || Rn > Rm = !(Rn < Rm)
EmitAluLoadOpers(context);
context.Emit(OpCodes.Clt_Un);
@ -102,7 +102,7 @@ namespace ChocolArm64.Instructions
public static void EmitSubsVCheck(ILEmitterCtx context)
{
//V = (Rd ^ Rn) & (Rn ^ Rm) < 0
// V = (Rd ^ Rn) & (Rn ^ Rm) < 0
context.Emit(OpCodes.Dup);
EmitAluLoadRn(context);
@ -170,7 +170,7 @@ namespace ChocolArm64.Instructions
{
switch (context.CurrOp)
{
//ARM32.
// ARM32.
case OpCode32AluImm op:
context.EmitLdc_I4(op.Imm);
@ -190,7 +190,7 @@ namespace ChocolArm64.Instructions
context.EmitLdc_I4(op.Imm);
break;
//ARM64.
// ARM64.
case IOpCodeAluImm64 op:
context.EmitLdc_I(op.Imm);
break;
@ -245,7 +245,7 @@ namespace ChocolArm64.Instructions
context.EmitStflg((int)PState.NBit);
}
//ARM32 helpers.
// ARM32 helpers.
private static void EmitLoadRmShiftedByImmediate(ILEmitterCtx context, OpCode32AluRsImm op, bool setCarry)
{
int shift = op.Imm;
@ -432,7 +432,7 @@ namespace ChocolArm64.Instructions
private static void EmitRrxC(ILEmitterCtx context, bool setCarry)
{
//Rotate right by 1 with carry.
// Rotate right by 1 with carry.
if (setCarry)
{
context.Emit(OpCodes.Dup);

4
ChocolArm64/Instructions/InstEmitBfm.cs
View file

@ -13,7 +13,7 @@ namespace ChocolArm64.Instructions
if (op.Pos < op.Shift)
{
//BFI.
// BFI.
context.EmitLdintzr(op.Rn);
int shift = op.GetBitsCount() - op.Shift;
@ -39,7 +39,7 @@ namespace ChocolArm64.Instructions
}
else
{
//BFXIL.
// BFXIL.
context.EmitLdintzr(op.Rn);
context.EmitLsr(op.Shift);

4
ChocolArm64/Instructions/InstEmitException.cs
View file

@ -31,8 +31,8 @@ namespace ChocolArm64.Instructions
context.EmitPrivateCall(typeof(CpuThreadState), mthdName);
//Check if the thread should still be running, if it isn't then we return 0
//to force a return to the dispatcher and then exit the thread.
// Check if the thread should still be running, if it isn't then we return 0
// to force a return to the dispatcher and then exit the thread.
context.EmitLdarg(TranslatedSub.StateArgIdx);
context.EmitCallPropGet(typeof(CpuThreadState), nameof(CpuThreadState.Running));

4
ChocolArm64/Instructions/InstEmitFlow32.cs
View file

@ -66,8 +66,8 @@ namespace ChocolArm64.Instructions
context.EmitStint(GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr));
//If x is true, then this is a branch with link and exchange.
//In this case we need to swap the mode between Arm <-> Thumb.
// If x is true, then this is a branch with link and exchange.
// In this case we need to swap the mode between Arm <-> Thumb.
if (x)
{
context.EmitLdc_I4(isThumb ? 0 : 1);

16
ChocolArm64/Instructions/InstEmitFlowHelper.cs
View file

@ -90,10 +90,10 @@ namespace ChocolArm64.Instructions
if (isJump)
{
//The tail prefix allows the JIT to jump to the next function,
//while releasing the stack space used by the current one.
//This is ideal for BR ARM instructions, which are
//basically indirect tail calls.
// The tail prefix allows the JIT to jump to the next function,
// while releasing the stack space used by the current one.
// This is ideal for BR ARM instructions, which are
// basically indirect tail calls.
context.Emit(OpCodes.Tailcall);
}
@ -114,10 +114,10 @@ namespace ChocolArm64.Instructions
private static void EmitContinueOrReturnCheck(ILEmitterCtx context)
{
//Note: The return value of the called method will be placed
//at the Stack, the return value is always a Int64 with the
//return address of the function. We check if the address is
//correct, if it isn't we keep returning until we reach the dispatcher.
// Note: The return value of the called method will be placed
// at the Stack, the return value is always a Int64 with the
// return address of the function. We check if the address is
// correct, if it isn't we keep returning until we reach the dispatcher.
if (context.CurrBlock.Next != null)
{
context.Emit(OpCodes.Dup);

8
ChocolArm64/Instructions/InstEmitMemory.cs
View file

@ -192,7 +192,7 @@ namespace ChocolArm64.Instructions
if (!op.PostIdx)
{
//Pre-indexing.
// Pre-indexing.
context.EmitLdc_I(op.Imm);
context.Emit(OpCodes.Add);
@ -213,7 +213,7 @@ namespace ChocolArm64.Instructions
break;
}
//Save address to Scratch var since the register value may change.
// Save address to Scratch var since the register value may change.
context.Emit(OpCodes.Dup);
context.EmitSttmp();
@ -221,8 +221,8 @@ namespace ChocolArm64.Instructions
private static void EmitWBackIfNeeded(ILEmitterCtx context)
{
//Check whenever the current OpCode has post-indexed write back, if so write it.
//Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both.
// Check whenever the current OpCode has post-indexed write back, if so write it.
// Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both.
if (context.CurrOp is OpCodeMemImm64 op && op.WBack)
{
context.EmitLdtmp();

22
ChocolArm64/Instructions/InstEmitMemory32.cs
View file

@ -137,15 +137,15 @@ namespace ChocolArm64.Instructions
EmitWriteCall(context, WordSizeLog2);
//Note: If Rn is also specified on the register list,
//and Rn is the first register on this list, then the
//value that is written to memory is the unmodified value,
//before the write back. If it is on the list, but it's
//not the first one, then the value written to memory
//varies between CPUs.
// Note: If Rn is also specified on the register list,
// and Rn is the first register on this list, then the
// value that is written to memory is the unmodified value,
// before the write back. If it is on the list, but it's
// not the first one, then the value written to memory
// varies between CPUs.
if (offset == 0 && op.PostOffset != 0)
{
//Emit write back after the first write.
// Emit write back after the first write.
EmitLoadFromRegister(context, op.Rn);
context.EmitLdc_I4(op.PostOffset);
@ -233,7 +233,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Brtrue_S, lblBigEndian);
//Little endian mode.
// Little endian mode.
context.Emit(OpCodes.Conv_U4);
EmitStoreToRegister(context, op.Rt);
@ -246,7 +246,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Br_S, lblEnd);
//Big endian mode.
// Big endian mode.
context.MarkLabel(lblBigEndian);
context.EmitLsr(32);
@ -288,7 +288,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Brtrue_S, lblBigEndian);
//Little endian mode.
// Little endian mode.
EmitLoadFromRegister(context, op.Rt | 1);
context.Emit(OpCodes.Conv_U8);
@ -299,7 +299,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Br_S, lblEnd);
//Big endian mode.
// Big endian mode.
context.MarkLabel(lblBigEndian);
context.EmitLsl(32);

42
ChocolArm64/Instructions/InstEmitMemoryEx.cs
View file

@ -89,10 +89,10 @@ namespace ChocolArm64.Instructions
if (pair)
{
//Exclusive loads should be atomic. For pairwise loads, we need to
//read all the data at once. For a 32-bits pairwise load, we do a
//simple 64-bits load, for a 128-bits load, we need to call a special
//method to read 128-bits atomically.
// Exclusive loads should be atomic. For pairwise loads, we need to
// read all the data at once. For a 32-bits pairwise load, we do a
// simple 64-bits load, for a 128-bits load, we need to call a special
// method to read 128-bits atomically.
if (op.Size == 2)
{
context.EmitLdtmp();
@ -101,7 +101,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Dup);
//Mask low half.
// Mask low half.
context.Emit(OpCodes.Conv_U4);
if (exclusive)
@ -111,7 +111,7 @@ namespace ChocolArm64.Instructions
context.EmitStintzr(op.Rt);
//Shift high half.
// Shift high half.
context.EmitLsr(32);
context.Emit(OpCodes.Conv_U4);
@ -131,7 +131,7 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Dup);
//Load low part of the vector.
// Load low part of the vector.
context.EmitLdc_I4(0);
context.EmitLdc_I4(3);
@ -144,7 +144,7 @@ namespace ChocolArm64.Instructions
context.EmitStintzr(op.Rt);
//Load high part of the vector.
// Load high part of the vector.
context.EmitLdc_I4(1);
context.EmitLdc_I4(3);
@ -164,7 +164,7 @@ namespace ChocolArm64.Instructions
}
else
{
//8, 16, 32 or 64-bits (non-pairwise) load.
// 8, 16, 32 or 64-bits (non-pairwise) load.
context.EmitLdtmp();
EmitReadZxCall(context, op.Size);
@ -180,7 +180,7 @@ namespace ChocolArm64.Instructions
public static void Pfrm(ILEmitterCtx context)
{
//Memory Prefetch, execute as no-op.
// Memory Prefetch, execute as no-op.
}
public static void Stlr(ILEmitterCtx context) => EmitStr(context, AccessType.Ordered);
@ -223,13 +223,13 @@ namespace ChocolArm64.Instructions
context.Emit(OpCodes.Brtrue_S, lblEx);
//Address check failed, set error right away and do not store anything.
// Address check failed, set error right away and do not store anything.
context.EmitLdc_I4(1);
context.EmitStintzr(op.Rs);
context.Emit(OpCodes.Br, lblEnd);
//Address check passsed.
// Address check passed.
context.MarkLabel(lblEx);
context.EmitLdarg(TranslatedSub.MemoryArgIdx);
@ -241,7 +241,7 @@ namespace ChocolArm64.Instructions
void EmitCast()
{
//The input should be always int64.
// The input should be always int64.
switch (op.Size)
{
case 0: context.Emit(OpCodes.Conv_U1); break;
@ -293,10 +293,10 @@ namespace ChocolArm64.Instructions
}
}
//The value returned is a bool, true if the values compared
//were equal and the new value was written, false otherwise.
//We need to invert this result, as on ARM 1 indicates failure,
//and 0 success on those instructions.
// The value returned is a bool, true if the values compared
// were equal and the new value was written, false otherwise.
// We need to invert this result, as on ARM 1 indicates failure,
// and 0 success on those instructions.
context.EmitLdc_I4(1);
context.Emit(OpCodes.Xor);
@ -305,7 +305,7 @@ namespace ChocolArm64.Instructions
context.EmitStintzr(op.Rs);
//Only clear the exclusive monitor if the store was successful (Rs = false).
// Only clear the exclusive monitor if the store was successful (Rs = false).
context.Emit(OpCodes.Brtrue_S, lblEnd);
Clrex(context);
@ -341,9 +341,9 @@ namespace ChocolArm64.Instructions
private static void EmitBarrier(ILEmitterCtx context)
{
//Note: This barrier is most likely not necessary, and probably
//doesn't make any difference since we need to do a ton of stuff
//(software MMU emulation) to read or write anything anyway.
// Note: This barrier is most likely not necessary, and probably
// doesn't make any difference since we need to do a ton of stuff
// (software MMU emulation) to read or write anything anyway.
context.EmitCall(typeof(Thread), nameof(Thread.MemoryBarrier));
}
}

6
ChocolArm64/Instructions/InstEmitMemoryHelper.cs
View file

@ -40,7 +40,7 @@ namespace ChocolArm64.Instructions
private static void EmitReadCall(ILEmitterCtx context, Extension ext, int size)
{
//Save the address into a temp.
// Save the address into a temp.
context.EmitStint(_tempIntAddress);
bool isSimd = IsSimd(context);
@ -99,7 +99,7 @@ namespace ChocolArm64.Instructions
{
bool isSimd = IsSimd(context);
//Save the value into a temp.
// Save the value into a temp.
if (isSimd)
{
context.EmitStvec(_tempVecValue);
@ -109,7 +109,7 @@ namespace ChocolArm64.Instructions
context.EmitStint(_tempIntValue);
}
//Save the address into a temp.
// Save the address into a temp.
context.EmitStint(_tempIntAddress);
if (size < 0 || size > (isSimd ? 4 : 3))

4
ChocolArm64/Instructions/InstEmitSimdHelper.cs
View file

@ -1298,8 +1298,8 @@ namespace ChocolArm64.Instructions
{
if (Optimizations.UseSse41 && size == 0)
{
//If the type is float, we can perform insertion and
//zero the upper bits with a single instruction (INSERTPS);
// If the type is float, we can perform insertion and
// zero the upper bits with a single instruction (INSERTPS);
context.EmitLdvec(reg);
VectorHelper.EmitCall(context, nameof(VectorHelper.Sse41VectorInsertScalarSingle));

2
ChocolArm64/Instructions/InstEmitSimdMemory.cs
View file

@ -96,7 +96,7 @@ namespace ChocolArm64.Instructions
if (op.Replicate)
{
//Only loads uses the replicate mode.
// Only loads uses the replicate mode.
if (!isLoad)
{
throw new InvalidOperationException();

16
ChocolArm64/Instructions/InstEmitSystem.cs
View file

@ -11,12 +11,12 @@ namespace ChocolArm64.Instructions
{
public static void Hint(ILEmitterCtx context)
{
//Execute as no-op.
// Execute as no-op.
}
public static void Isb(ILEmitterCtx context)
{
//Execute as no-op.
// Execute as no-op.
}
public static void Mrs(ILEmitterCtx context)
@ -85,21 +85,21 @@ namespace ChocolArm64.Instructions
public static void Nop(ILEmitterCtx context)
{
//Do nothing.
// Do nothing.
}
public static void Sys(ILEmitterCtx context)
{
//This instruction is used to do some operations on the CPU like cache invalidation,
//address translation and the like.
//We treat it as no-op here since we don't have any cache being emulated anyway.
// This instruction is used to do some operations on the CPU like cache invalidation,
// address translation and the like.
// We treat it as no-op here since we don't have any cache being emulated anyway.
OpCodeSystem64 op = (OpCodeSystem64)context.CurrOp;
switch (GetPackedId(op))
{
case 0b11_011_0111_0100_001:
{
//DC ZVA
// DC ZVA
for (int offs = 0; offs < (4 << CpuThreadState.DczSizeLog2); offs += 8)
{
context.EmitLdintzr(op.Rt);
@ -115,7 +115,7 @@ namespace ChocolArm64.Instructions
break;
}
//No-op
// No-op
case 0b11_011_0111_1110_001: //DC CIVAC
break;
}

8
ChocolArm64/Instructions/VectorHelper.cs
View file

@ -583,9 +583,9 @@ namespace ChocolArm64.Instructions
{
if (Sse41.IsSupported)
{
//Note: The if/else if is necessary to enable the JIT to
//produce a single INSERTPS instruction instead of the
//jump table fallback.
// Note: The if/else if is necessary to enable the JIT to
// produce a single INSERTPS instruction instead of the
// jump table fallback.
if (index == 0)
{
return Sse41.Insert(vector, value, 0x00);
@ -628,7 +628,7 @@ namespace ChocolArm64.Instructions
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static Vector128<float> Sse41VectorInsertScalarSingle(float value, Vector128<float> vector)
{
//Note: 0b1110 is the mask to zero the upper bits.
// Note: 0b1110 is the mask to zero the upper bits.
return Sse41.Insert(vector, value, 0b1110);
}