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CPU: Implement VFNMS.F32/64 (#1758)

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* Add necessary methods / op-code

* Enable Support for FMA Instruction Set

* Add Intrinsics / Assembly Opcodes for VFMSUB231XX.

* Add X86 Instructions for VFMSUB231XX

* Implement VFNMS

* Implement VFNMS Tests

* Add special cases for FMA instructions.

* Update PPTC Version

* Remove unused Op

* Move Check into Assert / Cleanup

* Rename and cleanup

* Whitespace

* Whitespace / Rename

* Re-sort

* Address final requests

* Implement VFMA.F64

* Simplify switch

* Simplify FMA Instructions into their own IntrinsicType.

* Remove whitespace

* Fix indentation

* Change tests for Vfnms -- disable inf / nan

* Move args up, not description ;)

* Undo vfma

* Completely remove vfms code.,

* Fix order of instruction in assembler
This commit is contained in:
sharmander 2020-12-03 14:20:02 -05:00 • committed by GitHub
parent c00d39b675
commit b479a43939
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GPG key ID: 4AEE18F83AFDEB23
14 changed files with 462 additions and 363 deletions
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20
ARMeilleure/CodeGen/X86/CodeGenerator.cs
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@ -406,12 +406,9 @@ namespace ARMeilleure.CodeGen.X86
else
{
EnsureSameReg(dest, src1);
Debug.Assert(src3.GetRegister().Index == 0);
context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
}
break;
}
@ -435,6 +432,23 @@ namespace ARMeilleure.CodeGen.X86
break;
}
case IntrinsicType.Fma:
{
Operand dest = operation.Destination;
Operand src1 = operation.GetSource(0);
Operand src2 = operation.GetSource(1);
Operand src3 = operation.GetSource(2);
EnsureSameType(dest, src1, src2, src3);
EnsureSameReg(dest, src1);
Debug.Assert(!dest.Type.IsInteger());
Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
context.Assembler.WriteInstruction(info.Inst, dest, src2, src3);
break;
}
}
}
else