Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
* Update CpuTest.cs * Delete CpuTestSimdCmp.cs Obsolete. * Update CpuTestSimdArithmetic.cs Superseded. * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update ASoftFloat.cs * Nit. * Update AOpCodeTable.cs * Update AOptimizations.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFloat.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFloat.cs * Update CpuTestSimdReg.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFloat.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs
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LDj3SNuD
gdkchan
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commit
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10 changed files with 2471 additions and 1162 deletions
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@ -81,14 +81,14 @@ namespace Ryujinx.Tests.Cpu
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private static IEnumerable<ulong> _1S_F_()
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{
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max SubNormal
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yield return 0x0000000080000001ul; // -Min SubNormal
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x00000000807FFFFFul; // -Max Subnormal
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yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x00000000007FFFFFul; // +Max SubNormal
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yield return 0x0000000000000001ul; // +Min SubNormal
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yield return 0x00000000007FFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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@ -104,17 +104,17 @@ namespace Ryujinx.Tests.Cpu
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if (!NoNaNs)
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{
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yield return 0x00000000FFFFFFFFul; // -QNaN (all ones payload)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FFFFFFFul; // +QNaN (all ones payload)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong Rnd1 = GenNormal_S();
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ulong Rnd2 = GenSubNormal_S();
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ulong Rnd2 = GenSubnormal_S();
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yield return (Grbg << 32) | Rnd1;
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yield return (Grbg << 32) | Rnd2;
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@ -123,14 +123,14 @@ namespace Ryujinx.Tests.Cpu
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private static IEnumerable<ulong> _2S_F_()
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{
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yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x8080000080800000ul; // -Min Normal
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yield return 0x807FFFFF807FFFFFul; // -Max SubNormal
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yield return 0x8000000180000001ul; // -Min SubNormal
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yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x807FFFFF807FFFFFul; // -Max Subnormal
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yield return 0x8000000180000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0080000000800000ul; // +Min Normal
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yield return 0x007FFFFF007FFFFFul; // +Max SubNormal
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yield return 0x0000000100000001ul; // +Min SubNormal
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yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
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yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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@ -146,16 +146,16 @@ namespace Ryujinx.Tests.Cpu
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if (!NoNaNs)
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{
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yield return 0xFFFFFFFFFFFFFFFFul; // -QNaN (all ones payload)
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yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FFFFFFF7FFFFFFFul; // +QNaN (all ones payload)
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yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
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yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FC000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Rnd1 = GenNormal_S();
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ulong Rnd2 = GenSubNormal_S();
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ulong Rnd2 = GenSubnormal_S();
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yield return (Rnd1 << 32) | Rnd1;
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yield return (Rnd2 << 32) | Rnd2;
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@ -164,14 +164,14 @@ namespace Ryujinx.Tests.Cpu
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private static IEnumerable<ulong> _1D_F_()
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{
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
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yield return 0x8010000000000000ul; // -Min Normal
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yield return 0x800FFFFFFFFFFFFFul; // -Max SubNormal
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yield return 0x8000000000000001ul; // -Min SubNormal
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yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
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yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
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yield return 0x8000000000000001ul; // -Min Subnormal (-double.Epsilon)
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yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
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yield return 0x0010000000000000ul; // +Min Normal
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yield return 0x000FFFFFFFFFFFFFul; // +Max SubNormal
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yield return 0x0000000000000001ul; // +Min SubNormal
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yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
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if (!NoZeros)
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{
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@ -187,16 +187,16 @@ namespace Ryujinx.Tests.Cpu
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if (!NoNaNs)
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{
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yield return 0xFFFFFFFFFFFFFFFFul; // -QNaN (all ones payload)
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yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FFFFFFFFFFFFFFFul; // +QNaN (all ones payload)
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yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
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yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
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yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
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yield return 0x7FF8000000000000ul; // +QNaN (all zeros payload) (-double.NaN) (DefaultNaN)
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yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
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}
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Rnd1 = GenNormal_D();
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ulong Rnd2 = GenSubNormal_D();
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ulong Rnd2 = GenSubnormal_D();
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yield return Rnd1;
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yield return Rnd2;
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@ -248,6 +248,40 @@ namespace Ryujinx.Tests.Cpu
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0x6EE1B800u // FCVTZU V0.2D, V0.2D
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};
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}
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private static uint[] _F_RecpX_Sqrt_S_S_()
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{
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return new uint[]
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{
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0x5EA1F820u, // FRECPX S0, S1
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0x1E21C020u // FSQRT S0, S1
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};
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}
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private static uint[] _F_RecpX_Sqrt_S_D_()
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{
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return new uint[]
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{
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0x5EE1F820u, // FRECPX D0, D1
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0x1E61C020u // FSQRT D0, D1
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};
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}
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private static uint[] _F_Sqrt_V_2S_4S_()
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{
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return new uint[]
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{
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0x2EA1F800u // FSQRT V0.2S, V0.2S
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};
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}
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private static uint[] _F_Sqrt_V_2D_()
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{
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return new uint[]
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{
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0x6EE1F800u // FSQRT V0.2D, V0.2D
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};
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}
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#endregion
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private const int RndCnt = 2;
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@ -754,21 +788,15 @@ namespace Ryujinx.Tests.Cpu
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[Test, Pairwise, Description("FCVT <Dd>, <Sn>")]
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public void Fcvt_S_SD([ValueSource("_1S_F_")] ulong A)
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{
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//const int DNFlagBit = 25; // Default NaN mode control bit.
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x1E22C020; // FCVT D0, S1
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE1(Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << DNFlagBit; // Any operation involving one or more NaNs returns the Default NaN.
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//Fpcr |= 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVT <Sd>, <Dn>")]
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@ -789,17 +817,13 @@ namespace Ryujinx.Tests.Cpu
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public void F_Cvt_NZ_SU_S_S([ValueSource("_F_Cvt_NZ_SU_S_S_")] uint Opcodes,
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[ValueSource("_1S_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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@ -851,6 +875,76 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void F_RecpX_Sqrt_S_S([ValueSource("_F_RecpX_Sqrt_S_S_")] uint Opcodes,
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[ValueSource("_1S_F_")] ulong A)
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{
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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int Fpcr = (int)TestContext.CurrentContext.Random.NextUInt() & (1 << (int)FPCR.DN);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, Fpcr: Fpcr);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC);
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}
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[Test, Pairwise]
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public void F_RecpX_Sqrt_S_D([ValueSource("_F_RecpX_Sqrt_S_D_")] uint Opcodes,
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[ValueSource("_1D_F_")] ulong A)
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{
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE1(Z);
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Vector128<float> V1 = MakeVectorE0(A);
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int Fpcr = (int)TestContext.CurrentContext.Random.NextUInt() & (1 << (int)FPCR.DN);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, Fpcr: Fpcr);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC);
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}
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[Test, Pairwise]
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public void F_Sqrt_V_2S_4S([ValueSource("_F_Sqrt_V_2S_4S_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcodes |= ((Q & 1) << 30);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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int Fpcr = (int)TestContext.CurrentContext.Random.NextUInt() & (1 << (int)FPCR.DN);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, Fpcr: Fpcr);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC);
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}
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[Test, Pairwise]
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public void F_Sqrt_V_2D([ValueSource("_F_Sqrt_V_2D_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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int Fpcr = (int)TestContext.CurrentContext.Random.NextUInt() & (1 << (int)FPCR.DN);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, Fpcr: Fpcr);
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CompareAgainstUnicorn(FpsrMask: FPSR.IOC);
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}
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[Test, Pairwise, Description("NEG <V><d>, <V><n>")]
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public void Neg_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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