Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
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gdkchan
GitHub
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29 changed files with 686 additions and 87 deletions
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@ -168,9 +168,59 @@ namespace ChocolArm64.Decoders
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{
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//Note: On ARM32, most ALU operations can write to R15 (PC),
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//so we must consider such operations as a branch in potential aswell.
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return opCode is IOpCodeBImm32 ||
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opCode is IOpCodeBReg32 ||
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(opCode is IOpCodeAlu32 op && op.Rd == RegisterAlias.Aarch32Pc);
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if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
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{
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return true;
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}
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//Same thing for memory operations. We have the cases where PC is a target
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//register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
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//a write back to PC (wback == true && Rn == 15), however the later may
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//be "undefined" depending on the CPU, so compilers should not produce that.
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if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
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{
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int rt, rn;
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bool wBack, isLoad;
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if (opCode is IOpCode32Mem opMem)
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{
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rt = opMem.Rt;
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rn = opMem.Rn;
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wBack = opMem.WBack;
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isLoad = opMem.IsLoad;
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//For the dual load, we also need to take into account the
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//case were Rt2 == 15 (PC).
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if (rt == 14 && opMem.Emitter == InstEmit32.Ldrd)
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{
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rt = RegisterAlias.Aarch32Pc;
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}
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}
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else if (opCode is IOpCode32MemMult opMemMult)
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{
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const int pcMask = 1 << RegisterAlias.Aarch32Pc;
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rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
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rn = opMemMult.Rn;
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wBack = opMemMult.PostOffset != 0;
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isLoad = opMemMult.IsLoad;
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}
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else
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{
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throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
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}
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if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
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(rn == RegisterAlias.Aarch32Pc && wBack))
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{
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return true;
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}
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}
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//Explicit branch instructions.
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return opCode is IOpCode32BImm ||
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opCode is IOpCode32BReg;
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}
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private static bool IsException(OpCode64 opCode)
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@ -1,6 +1,6 @@
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namespace ChocolArm64.Decoders
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{
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interface IOpCodeAlu32 : IOpCode32
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interface IOpCode32Alu : IOpCode32
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{
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int Rd { get; }
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int Rn { get; }
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4
ChocolArm64/Decoders/IOpCode32BImm.cs
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4
ChocolArm64/Decoders/IOpCode32BImm.cs
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@ -0,0 +1,4 @@
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namespace ChocolArm64.Decoders
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{
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interface IOpCode32BImm : IOpCode32, IOpCodeBImm { }
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}
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@ -1,6 +1,6 @@
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namespace ChocolArm64.Decoders
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{
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interface IOpCodeBReg32 : IOpCode32
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interface IOpCode32BReg : IOpCode32
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{
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int Rm { get; }
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}
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12
ChocolArm64/Decoders/IOpCode32Mem.cs
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12
ChocolArm64/Decoders/IOpCode32Mem.cs
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@ -0,0 +1,12 @@
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namespace ChocolArm64.Decoders
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{
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interface IOpCode32Mem : IOpCode32
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{
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int Rt { get; }
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int Rn { get; }
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bool WBack { get; }
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bool IsLoad { get; }
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}
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}
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13
ChocolArm64/Decoders/IOpCode32MemMult.cs
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13
ChocolArm64/Decoders/IOpCode32MemMult.cs
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@ -0,0 +1,13 @@
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namespace ChocolArm64.Decoders
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{
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interface IOpCode32MemMult : IOpCode32
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{
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int Rn { get; }
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int RegisterMask { get; }
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int PostOffset { get; }
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bool IsLoad { get; }
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}
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}
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@ -1,4 +0,0 @@
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namespace ChocolArm64.Decoders
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{
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interface IOpCodeBImm32 : IOpCode32, IOpCodeBImm { }
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}
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@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeAlu32 : OpCode32, IOpCodeAlu32
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class OpCode32Alu : OpCode32, IOpCode32Alu
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{
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public int Rd { get; private set; }
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public int Rn { get; private set; }
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public bool SetFlags { get; private set; }
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public OpCodeAlu32(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCode32Alu(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rd = (opCode >> 12) & 0xf;
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Rn = (opCode >> 16) & 0xf;
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@ -2,13 +2,13 @@ using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeAluImm32 : OpCodeAlu32
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class OpCode32AluImm : OpCode32Alu
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{
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public int Imm { get; private set; }
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public bool IsRotated { get; private set; }
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public OpCodeAluImm32(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCode32AluImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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int value = (opCode >> 0) & 0xff;
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int shift = (opCode >> 8) & 0xf;
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@ -2,14 +2,14 @@ using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeAluRsImm32 : OpCodeAlu32
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class OpCode32AluRsImm : OpCode32Alu
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{
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public int Rm { get; private set; }
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public int Imm { get; private set; }
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public ShiftType ShiftType { get; private set; }
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public OpCodeAluRsImm32(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCode32AluRsImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rm = (opCode >> 0) & 0xf;
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Imm = (opCode >> 7) & 0x1f;
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@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeBImm32 : OpCode32, IOpCodeBImm32
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class OpCode32BImm : OpCode32, IOpCode32BImm
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{
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public long Imm { get; private set; }
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public OpCodeBImm32(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCode32BImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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uint pc = GetPc();
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@ -2,11 +2,11 @@ using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeBReg32 : OpCode32, IOpCodeBReg32
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class OpCode32BReg : OpCode32, IOpCode32BReg
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{
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public int Rm { get; private set; }
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public OpCodeBReg32(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCode32BReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rm = opCode & 0xf;
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}
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37
ChocolArm64/Decoders/OpCode32Mem.cs
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37
ChocolArm64/Decoders/OpCode32Mem.cs
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@ -0,0 +1,37 @@
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using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCode32Mem : OpCode32, IOpCode32Mem
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{
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public int Rt { get; private set; }
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public int Rn { get; private set; }
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public int Imm { get; protected set; }
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public bool Index { get; private set; }
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public bool Add { get; private set; }
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public bool WBack { get; private set; }
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public bool Unprivileged { get; private set; }
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public bool IsLoad { get; private set; }
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public OpCode32Mem(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rt = (opCode >> 12) & 0xf;
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Rn = (opCode >> 16) & 0xf;
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bool isLoad = (opCode & (1 << 20)) != 0;
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bool w = (opCode & (1 << 21)) != 0;
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bool u = (opCode & (1 << 23)) != 0;
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bool p = (opCode & (1 << 24)) != 0;
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Index = p;
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Add = u;
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WBack = !p || w;
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Unprivileged = !p && w;
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IsLoad = isLoad || inst.Emitter == InstEmit32.Ldrd;
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}
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}
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}
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12
ChocolArm64/Decoders/OpCode32MemImm.cs
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12
ChocolArm64/Decoders/OpCode32MemImm.cs
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@ -0,0 +1,12 @@
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using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCode32MemImm : OpCode32Mem
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{
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public OpCode32MemImm(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Imm = opCode & 0xfff;
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}
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}
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}
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15
ChocolArm64/Decoders/OpCode32MemImm8.cs
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15
ChocolArm64/Decoders/OpCode32MemImm8.cs
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@ -0,0 +1,15 @@
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using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCode32MemImm8 : OpCode32Mem
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{
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public OpCode32MemImm8(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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int imm4L = (opCode >> 0) & 0xf;
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int imm4H = (opCode >> 8) & 0xf;
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Imm = imm4L | (imm4H << 4);
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}
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}
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}
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57
ChocolArm64/Decoders/OpCode32MemMult.cs
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57
ChocolArm64/Decoders/OpCode32MemMult.cs
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@ -0,0 +1,57 @@
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using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCode32MemMult : OpCode32, IOpCode32MemMult
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{
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public int Rn { get; private set; }
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public int RegisterMask { get; private set; }
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public int Offset { get; private set; }
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public int PostOffset { get; private set; }
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public bool IsLoad { get; private set; }
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public OpCode32MemMult(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rn = (opCode >> 16) & 0xf;
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bool isLoad = (opCode & (1 << 20)) != 0;
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bool w = (opCode & (1 << 21)) != 0;
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bool u = (opCode & (1 << 23)) != 0;
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bool p = (opCode & (1 << 24)) != 0;
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RegisterMask = opCode & 0xffff;
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int regsSize = 0;
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for (int index = 0; index < 16; index++)
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{
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regsSize += (RegisterMask >> index) & 1;
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}
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regsSize *= 4;
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if (!u)
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{
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Offset -= regsSize;
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}
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if (u == p)
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{
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Offset += 4;
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}
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if (w)
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{
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PostOffset = u ? regsSize : -regsSize;
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}
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else
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{
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PostOffset = 0;
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}
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IsLoad = isLoad;
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}
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}
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}
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@ -2,7 +2,7 @@ using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeAluImm8T16 : OpCodeT16, IOpCodeAlu32
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class OpCodeT16AluImm8 : OpCodeT16, IOpCode32Alu
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{
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private int _rdn;
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@ -13,7 +13,7 @@ namespace ChocolArm64.Decoders
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public int Imm { get; private set; }
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public OpCodeAluImm8T16(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCodeT16AluImm8(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Imm = (opCode >> 0) & 0xff;
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_rdn = (opCode >> 8) & 0x7;
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namespace ChocolArm64.Decoders
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{
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class OpCodeBRegT16 : OpCodeT16, IOpCodeBReg32
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class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
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{
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public int Rm { get; private set; }
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public OpCodeBRegT16(Inst inst, long position, int opCode) : base(inst, position, opCode)
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public OpCodeT16BReg(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rm = (opCode >> 3) & 0xf;
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}
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