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Implement some ARM32 memory instructions and CMP (#565)

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* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)

* Rename some opcode classes and flag masks for consistency

* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations

* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC

* Re-align arm32 instructions on the opcode table
This commit is contained in:
gdkchan 2019-01-29 13:06:11 -03:00 • committed by GitHub
parent 8f7fcede7f
commit c1bdf19061
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GPG key ID: 4AEE18F83AFDEB23
29 changed files with 686 additions and 87 deletions
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19
ChocolArm64/State/CpuThreadState.cs
View file

@ -13,8 +13,6 @@ namespace ChocolArm64.State
private const int MinInstForCheck = 4000000;
public bool Thumb;
public ulong X0, X1, X2, X3, X4, X5, X6, X7,
X8, X9, X10, X11, X12, X13, X14, X15,
X16, X17, X18, X19, X20, X21, X22, X23,
@ -25,13 +23,16 @@ namespace ChocolArm64.State
V16, V17, V18, V19, V20, V21, V22, V23,
V24, V25, V26, V27, V28, V29, V30, V31;
public bool Aarch32;
public bool Thumb;
public bool BigEndian;
public bool Overflow;
public bool Carry;
public bool Zero;
public bool Negative;
public bool IsAarch32;
public int ElrHyp;
public bool Running { get; set; }
@ -51,10 +52,10 @@ namespace ChocolArm64.State
{
get
{
return (Negative ? (int)PState.N : 0) |
(Zero ? (int)PState.Z : 0) |
(Carry ? (int)PState.C : 0) |
(Overflow ? (int)PState.V : 0);
return (Negative ? (int)PState.NMask : 0) |
(Zero ? (int)PState.ZMask : 0) |
(Carry ? (int)PState.CMask : 0) |
(Overflow ? (int)PState.VMask : 0);
}
}
@ -140,7 +141,7 @@ namespace ChocolArm64.State
internal ExecutionMode GetExecutionMode()
{
if (!IsAarch32)
if (!Aarch32)
{
return ExecutionMode.Aarch64;
}

17
ChocolArm64/State/PState.cs
View file

@ -6,22 +6,19 @@ namespace ChocolArm64.State
enum PState
{
TBit = 5,
EBit = 9,
VBit = 28,
CBit = 29,
ZBit = 30,
NBit = 31,
T = 1 << TBit,
TMask = 1 << TBit,
EMask = 1 << EBit,
V = 1 << VBit,
C = 1 << CBit,
Z = 1 << ZBit,
N = 1 << NBit,
Nz = N | Z,
Cv = C | V,
Nzcv = Nz | Cv
VMask = 1 << VBit,
CMask = 1 << CBit,
ZMask = 1 << ZBit,
NMask = 1 << NBit
}
}

1
ChocolArm64/State/Register.cs
View file

@ -44,6 +44,7 @@ namespace ChocolArm64.State
switch ((PState)Index)
{
case PState.TBit: return GetField(nameof(CpuThreadState.Thumb));
case PState.EBit: return GetField(nameof(CpuThreadState.BigEndian));
case PState.VBit: return GetField(nameof(CpuThreadState.Overflow));
case PState.CBit: return GetField(nameof(CpuThreadState.Carry));