Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)

* Add VEOR and AES instructions.

* Add tests for crypto instructions.

* Update ValueSource name.
This commit is contained in:
riperiperi 2020-03-13 23:29:58 +00:00 committed by GitHub
parent ff2bac9c90
commit dd433c1296
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
7 changed files with 239 additions and 14 deletions

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@ -0,0 +1,49 @@
using ARMeilleure.Decoders;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation;
using static ARMeilleure.Instructions.InstEmitHelper;
namespace ARMeilleure.Instructions
{
partial class InstEmit32
{
public static void Aesd_V(ArmEmitterContext context)
{
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
Operand d = GetVecA32(op.Qd);
Operand n = GetVecA32(op.Qm);
context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n));
}
public static void Aese_V(ArmEmitterContext context)
{
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
Operand d = GetVecA32(op.Qd);
Operand n = GetVecA32(op.Qm);
context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n));
}
public static void Aesimc_V(ArmEmitterContext context)
{
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
Operand n = GetVecA32(op.Qm);
context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n));
}
public static void Aesmc_V(ArmEmitterContext context)
{
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
Operand n = GetVecA32(op.Qm);
context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.MixColumns), n));
}
}
}

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@ -55,6 +55,18 @@ namespace ARMeilleure.Instructions
}
}
public static void Veor_I(ArmEmitterContext context)
{
if (Optimizations.UseSse2)
{
EmitVectorBinaryOpF32(context, Intrinsic.X86Pxor, Intrinsic.X86Pxor);
}
else
{
EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseExclusiveOr(op1, op2));
}
}
public static void Vorr_I(ArmEmitterContext context)
{
if (Optimizations.UseSse2)

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@ -547,6 +547,7 @@ namespace ARMeilleure.Instructions
Vcvt,
Vdiv,
Vdup,
Veor,
Vext,
Vld1,
Vld2,