Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions * Improve test descriptions * Rename SMULH to SMUL__ * Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions * Fix new tests * Replace AND 0xFFFF with 16-bits zero extension (more efficient)
This commit is contained in:
gdkchan
GitHub
parent
b8ee5b15ab
commit
fb0939f9b6
12 changed files with 666 additions and 195 deletions
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@ -389,6 +389,20 @@ namespace ARMeilleure.Instructions
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EmitDiv(context, false);
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}
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public static void Ssat(ArmEmitterContext context)
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{
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OpCode32Sat op = (OpCode32Sat)context.CurrOp;
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EmitSat(context, -(1 << op.SatImm), (1 << op.SatImm) - 1);
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}
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public static void Ssat16(ArmEmitterContext context)
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{
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OpCode32Sat16 op = (OpCode32Sat16)context.CurrOp;
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EmitSat16(context, -(1 << op.SatImm), (1 << op.SatImm) - 1);
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}
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public static void Sub(ArmEmitterContext context)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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@ -460,6 +474,20 @@ namespace ARMeilleure.Instructions
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EmitDiv(context, true);
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}
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public static void Usat(ArmEmitterContext context)
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{
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OpCode32Sat op = (OpCode32Sat)context.CurrOp;
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EmitSat(context, 0, op.SatImm == 32 ? (int)(~0) : (1 << op.SatImm) - 1);
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}
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public static void Usat16(ArmEmitterContext context)
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{
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OpCode32Sat16 op = (OpCode32Sat16)context.CurrOp;
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EmitSat16(context, 0, (1 << op.SatImm) - 1);
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}
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public static void Uxtb(ArmEmitterContext context)
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{
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EmitSignExtend(context, false, 8);
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@ -553,7 +581,7 @@ namespace ARMeilleure.Instructions
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lowAdd = context.ZeroExtend16(OperandType.I32, n);
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highAdd = context.ZeroExtend16(OperandType.I32, context.ShiftRightUI(n, Const(16)));
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}
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low16 = context.Add(low16, lowAdd);
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high16 = context.Add(high16, highAdd);
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}
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@ -615,9 +643,116 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblEnd);
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}
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private static void EmitSat(ArmEmitterContext context, int intMin, int intMax)
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{
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OpCode32Sat op = (OpCode32Sat)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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int shift = DecodeImmShift(op.ShiftType, op.Imm5);
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switch (op.ShiftType)
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{
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case ShiftType.Lsl:
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if (shift == 32)
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{
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n = Const(0);
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}
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else
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{
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n = context.ShiftLeft(n, Const(shift));
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}
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break;
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case ShiftType.Asr:
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if (shift == 32)
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{
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n = context.ShiftRightSI(n, Const(31));
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}
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else
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{
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n = context.ShiftRightSI(n, Const(shift));
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}
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break;
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}
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Operand lblCheckLtIntMin = Label();
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Operand lblNoSat = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblCheckLtIntMin, context.ICompareGreater(n, Const(intMax)));
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SetFlag(context, PState.QFlag, Const(1));
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SetIntA32(context, op.Rd, Const(intMax));
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context.Branch(lblEnd);
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context.MarkLabel(lblCheckLtIntMin);
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context.BranchIfFalse(lblNoSat, context.ICompareLess(n, Const(intMin)));
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SetFlag(context, PState.QFlag, Const(1));
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SetIntA32(context, op.Rd, Const(intMin));
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context.Branch(lblEnd);
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context.MarkLabel(lblNoSat);
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SetIntA32(context, op.Rd, n);
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context.MarkLabel(lblEnd);
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}
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private static void EmitSat16(ArmEmitterContext context, int intMin, int intMax)
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{
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OpCode32Sat16 op = (OpCode32Sat16)context.CurrOp;
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void SetD(int part, Operand value)
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{
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if (part == 0)
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{
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SetIntA32(context, op.Rd, context.ZeroExtend16(OperandType.I32, value));
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}
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else
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{
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SetIntA32(context, op.Rd, context.BitwiseOr(GetIntA32(context, op.Rd), context.ShiftLeft(value, Const(16))));
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}
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}
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Operand n = GetIntA32(context, op.Rn);
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Operand nLow = context.SignExtend16(OperandType.I32, n);
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Operand nHigh = context.ShiftRightSI(n, Const(16));
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for (int part = 0; part < 2; part++)
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{
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Operand nPart = part == 0 ? nLow : nHigh;
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Operand lblCheckLtIntMin = Label();
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Operand lblNoSat = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblCheckLtIntMin, context.ICompareGreater(nPart, Const(intMax)));
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SetFlag(context, PState.QFlag, Const(1));
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SetD(part, Const(intMax));
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context.Branch(lblEnd);
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context.MarkLabel(lblCheckLtIntMin);
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context.BranchIfFalse(lblNoSat, context.ICompareLess(nPart, Const(intMin)));
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SetFlag(context, PState.QFlag, Const(1));
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SetD(part, Const(intMin));
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context.Branch(lblEnd);
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context.MarkLabel(lblNoSat);
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SetD(part, nPart);
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context.MarkLabel(lblEnd);
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}
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}
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private static void EmitAluStore(ArmEmitterContext context, Operand value)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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EmitGenericAluStoreA32(context, op.Rd, op.SetFlags, value);
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}
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}
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@ -297,6 +297,21 @@ namespace ARMeilleure.Instructions
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return m;
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}
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public static int DecodeImmShift(ShiftType shiftType, int shift)
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{
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if (shift == 0)
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{
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switch (shiftType)
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{
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case ShiftType.Lsr: shift = 32; break;
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case ShiftType.Asr: shift = 32; break;
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case ShiftType.Ror: shift = 1; break;
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}
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}
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return shift;
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}
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public static Operand GetMShiftedByReg(ArmEmitterContext context, OpCode32AluRsReg op, bool setCarry)
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{
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Operand m = GetIntA32(context, op.Rm);
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@ -328,7 +343,7 @@ namespace ARMeilleure.Instructions
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if (expected)
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{
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context.BranchIfFalse(endLabel, boolValue);
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}
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}
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else
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{
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context.BranchIfTrue(endLabel, boolValue);
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@ -411,7 +426,7 @@ namespace ARMeilleure.Instructions
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SetFlag(context, PState.CFlag, cOut);
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}, false);
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}
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return context.ConditionalSelect(shiftLarge, Const(0), result);
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}
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@ -1,5 +1,6 @@
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using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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@ -53,27 +54,6 @@ namespace ARMeilleure.Instructions
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EmitAluStore(context, res);
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}
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public static void Smull(ArmEmitterContext context)
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{
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OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
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Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
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Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
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Operand res = context.Multiply(n, m);
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Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
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Operand lo = context.ConvertI64ToI32(res);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
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EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
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}
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public static void Smmla(ArmEmitterContext context)
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{
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EmitSmmul(context, MullFlags.SignedAdd);
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@ -101,7 +81,7 @@ namespace ARMeilleure.Instructions
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if (flags.HasFlag(MullFlags.Add) && op.Ra != 0xf)
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{
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res = context.Add(context.ShiftLeft(context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Ra)), Const(32)), res);
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}
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}
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else if (flags.HasFlag(MullFlags.Subtract))
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{
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res = context.Subtract(context.ShiftLeft(context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Ra)), Const(32)), res);
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@ -117,37 +97,40 @@ namespace ARMeilleure.Instructions
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EmitGenericAluStoreA32(context, op.Rd, false, hi);
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}
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public static void Smlab(ArmEmitterContext context)
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public static void Smla__(ArmEmitterContext context)
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{
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OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand m = GetIntA32(context, op.Rm);
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Operand a = GetIntA32(context, op.Ra);
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if (op.NHigh)
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{
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n = context.SignExtend16(OperandType.I32, context.ShiftRightUI(n, Const(16)));
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n = context.SignExtend16(OperandType.I64, context.ShiftRightUI(n, Const(16)));
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}
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else
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{
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n = context.SignExtend16(OperandType.I32, n);
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n = context.SignExtend16(OperandType.I64, n);
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}
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if (op.MHigh)
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{
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m = context.SignExtend16(OperandType.I32, context.ShiftRightUI(m, Const(16)));
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m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
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}
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else
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{
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m = context.SignExtend16(OperandType.I32, m);
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m = context.SignExtend16(OperandType.I64, m);
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}
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Operand res = context.Multiply(n, m);
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Operand a = GetIntA32(context, op.Ra);
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res = context.Add(res, a);
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Operand toAdd = context.SignExtend32(OperandType.I64, a);
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res = context.Add(res, toAdd);
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Operand q = context.ICompareNotEqual(res, context.SignExtend32(OperandType.I64, res));
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res = context.ConvertI64ToI32(res);
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// TODO: set Q flag when last addition overflows (saturation)?
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UpdateQFlag(context, q);
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EmitGenericAluStoreA32(context, op.Rd, false, res);
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}
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@ -157,7 +140,7 @@ namespace ARMeilleure.Instructions
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EmitMlal(context, true);
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}
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public static void Smlalh(ArmEmitterContext context)
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public static void Smlal__(ArmEmitterContext context)
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{
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OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
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@ -167,7 +150,7 @@ namespace ARMeilleure.Instructions
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if (op.NHigh)
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{
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n = context.SignExtend16(OperandType.I64, context.ShiftRightUI(n, Const(16)));
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}
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}
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else
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{
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n = context.SignExtend16(OperandType.I64, n);
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@ -176,7 +159,7 @@ namespace ARMeilleure.Instructions
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if (op.MHigh)
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{
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m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
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}
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}
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else
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{
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m = context.SignExtend16(OperandType.I64, m);
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@ -195,7 +178,37 @@ namespace ARMeilleure.Instructions
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EmitGenericAluStoreA32(context, op.RdLo, false, lo);
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}
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public static void Smulh(ArmEmitterContext context)
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public static void Smlaw_(ArmEmitterContext context)
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{
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OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand m = GetIntA32(context, op.Rm);
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Operand a = GetIntA32(context, op.Ra);
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if (op.MHigh)
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{
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m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
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}
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else
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{
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m = context.SignExtend16(OperandType.I64, m);
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}
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Operand res = context.Multiply(context.SignExtend32(OperandType.I64, n), m);
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Operand toAdd = context.ShiftLeft(context.SignExtend32(OperandType.I64, a), Const(16));
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res = context.Add(res, toAdd);
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res = context.ShiftRightSI(res, Const(16));
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Operand q = context.ICompareNotEqual(res, context.SignExtend32(OperandType.I64, res));
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res = context.ConvertI64ToI32(res);
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UpdateQFlag(context, q);
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EmitGenericAluStoreA32(context, op.Rd, false, res);
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}
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public static void Smul__(ArmEmitterContext context)
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{
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OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
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@ -225,6 +238,51 @@ namespace ARMeilleure.Instructions
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EmitGenericAluStoreA32(context, op.Rd, false, res);
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}
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public static void Smull(ArmEmitterContext context)
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{
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OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
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Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
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Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
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Operand res = context.Multiply(n, m);
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Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
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Operand lo = context.ConvertI64ToI32(res);
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if (op.SetFlags)
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{
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EmitNZFlagsCheck(context, res);
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}
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EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
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EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
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}
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public static void Smulw_(ArmEmitterContext context)
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{
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OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
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Operand n = GetIntA32(context, op.Rn);
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Operand m = GetIntA32(context, op.Rm);
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if (op.MHigh)
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{
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m = context.SignExtend16(OperandType.I64, context.ShiftRightUI(m, Const(16)));
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}
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else
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{
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m = context.SignExtend16(OperandType.I64, m);
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}
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Operand res = context.Multiply(context.SignExtend32(OperandType.I64, n), m);
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res = context.ShiftRightUI(res, Const(16));
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res = context.ConvertI64ToI32(res);
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EmitGenericAluStoreA32(context, op.Rd, false, res);
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}
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public static void Umlal(ArmEmitterContext context)
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{
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EmitMlal(context, false);
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@ -286,5 +344,16 @@ namespace ARMeilleure.Instructions
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EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
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EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
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}
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private static void UpdateQFlag(ArmEmitterContext context, Operand q)
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{
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Operand lblSkipSetQ = Label();
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context.BranchIfFalse(lblSkipSetQ, q);
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SetFlag(context, PState.QFlag, Const(1));
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context.MarkLabel(lblSkipSetQ);
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}
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}
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}
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@ -81,8 +81,11 @@ namespace ARMeilleure.Instructions
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Sdiv,
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Smaddl,
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Smsubl,
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Smulh,
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Smul__,
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Smull,
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Smulw_,
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Ssat,
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Ssat16,
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Stlr,
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Stlxp,
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Stlxr,
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@ -491,9 +494,10 @@ namespace ARMeilleure.Instructions
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Rsb,
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Rsc,
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Sbfx,
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Smlab,
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Smla__,
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Smlal,
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Smlalh,
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Smlal__,
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Smlaw_,
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Smmla,
|
||||
Smmls,
|
||||
Smmul,
|
||||
|
|
@ -519,6 +523,8 @@ namespace ARMeilleure.Instructions
|
|||
Ubfx,
|
||||
Umlal,
|
||||
Umull,
|
||||
Usat,
|
||||
Usat16,
|
||||
Uxtb,
|
||||
Uxtb16,
|
||||
Uxth,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue