Merry
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1039797c30
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Implement Zip1, Zip2 (#25)
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2018-02-20 07:41:55 -03:00 |
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gdkchan
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770cb4b655
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Somewhat better scheduler I guess
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2018-02-19 16:37:13 -03:00 |
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gdkchan
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f35d286c8d
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Rename ARegisters to AThreadState
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2018-02-18 16:28:07 -03:00 |
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gdkchan
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5a0396efaf
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Minor cpu fixes
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2018-02-18 16:01:21 -03:00 |
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gdkchan
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3872ae034d
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Add MLS (vector) instruction, fix mistake introduced on last commit
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2018-02-18 02:13:42 -03:00 |
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gdkchan
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1c44d9f66d
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Fix for some SIMD issues
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2018-02-18 01:57:33 -03:00 |
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gdkchan
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595e7ee588
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Add FCVTAS and FCVTAU instructions
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2018-02-17 18:59:37 -03:00 |
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gdkchan
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161193e113
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CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements
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2018-02-17 18:06:11 -03:00 |
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Merry
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1bfe6a9c22
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Add some tests (#18)
* Add tests
* Add some simple Alu instruction tests
* travis: Run tests
* CpuTest: Add TearDown
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2018-02-15 21:04:38 -03:00 |
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gdkchan
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be1d01bf7d
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Shouldn't have undone this
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2018-02-15 01:35:44 -03:00 |
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gdkchan
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7c314eadcf
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Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)
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2018-02-15 01:32:25 -03:00 |
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Merry
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7c4346685c
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AInstEmitAluHelper: Simplify EmitAddsVCheck (#14)
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2018-02-14 19:01:36 -03:00 |
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Merry
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7791e1fe36
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AInstEmitAluHelper: Simplify EmitSubsCCheck (#15)
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2018-02-14 19:01:21 -03:00 |
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gdkchan
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7ed1153062
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Add SHRN instruction, and fix ADDV
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2018-02-14 02:43:21 -03:00 |
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gdkchan
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f68696dc4a
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Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments
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2018-02-13 23:43:08 -03:00 |
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gdkchan
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7d11a146c0
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Generate CIL for SCVTF (vector), add undefined encodings for some instructions
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2018-02-12 00:37:20 -03:00 |
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gdkchan
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55743c0cba
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Only throw undefined instruction exception at execution, not at translation stage
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2018-02-10 14:20:46 -03:00 |
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gdkchan
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9f612682e0
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Add BRK on the opcode table
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2018-02-10 12:16:48 -03:00 |
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gdkchan
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9063766ed6
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Add BRK instruction, fix wrong namespace on one of Am interfaces, and disable Debug/Trace logs by default
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2018-02-10 10:24:16 -03:00 |
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gdkchan
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7f4a190665
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Fixes to memory management
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2018-02-09 21:13:18 -03:00 |
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gdkchan
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ccc9ce1908
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Move a few more SIMD instructions to emit CIL directly instead of a method call
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2018-02-09 17:14:47 -03:00 |
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gdkchan
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6a3aa6cd88
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Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions
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2018-02-09 00:26:20 -03:00 |
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gdkchan
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ae91da5b60
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Merge pull request #2 from gdkchan/direct_memory
Removed parts of the MMU functionality to use memory directly (faster…
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2018-02-08 20:20:01 -03:00 |
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gdkchan
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64d34f2882
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Fix a copy-paste bug on Ins_V
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2018-02-07 21:53:23 -03:00 |
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gdkchan
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d0954564cd
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Add ADC and SBC instructions
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2018-02-07 20:46:36 -03:00 |
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gdkchan
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79f028e410
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Add FMADD and FMSUB instructions
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2018-02-07 20:07:16 -03:00 |
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gdkchan
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768b573772
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Add FMOV (scalar, register) and FCMPE instructions
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2018-02-07 19:43:52 -03:00 |
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gdkchan
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18ac1c4045
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Removed parts of the MMU functionality to use memory directly (faster, but potentially more dangerous, WIP), also changed the Shl/Sshr immediate instructions to use IL instead of calling the method
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2018-02-07 13:44:48 -03:00 |
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gdkchan
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d77d691381
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Implement SSHL instruction, fix exception on FMAX/FMIN, and use a better exception message for undefined/unimplemented instructions
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2018-02-07 09:38:43 -03:00 |
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gdkchan
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b99e808791
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Support loading NSO/NRO without a MOD0 header, stub some functions, support more ids on SvcGetInfo
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2018-02-06 20:28:32 -03:00 |
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gdkchan
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2347c44bbf
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Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method
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2018-02-06 12:15:08 -03:00 |
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gdkchan
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b7e1d9930d
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aloha
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2018-02-04 20:08:20 -03:00 |
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