34100051e4
* Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update Pseudocode.cs * Update Instructions.cs * Update Bits.cs * Update Integer.cs * Update AOpCodeTable.cs * Create AInstEmitSimdHash.cs * Update ASoftFallback.cs
661 lines
20 KiB
C#
661 lines
20 KiB
C#
using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Runtime.CompilerServices;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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namespace ChocolArm64.Instruction
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{
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using static AVectorHelper;
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static class ASoftFallback
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{
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public static void EmitCall(AILEmitterCtx Context, string MthdName)
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{
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Context.EmitCall(typeof(ASoftFallback), MthdName);
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}
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#region "Saturating"
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public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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long TMinValue = -(1L << (ESize - 1));
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return op;
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}
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}
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public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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ulong TMinValue = 0UL;
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if (op > (long)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else if (op < (long)TMinValue)
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{
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SetFpsrQCFlag(State);
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return TMinValue;
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}
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else
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{
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return (ulong)op;
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}
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}
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public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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long TMaxValue = (1L << (ESize - 1)) - 1L;
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if (op > (ulong)TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return (long)op;
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}
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}
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public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State)
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{
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int ESize = 8 << Size;
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ulong TMaxValue = (1UL << ESize) - 1UL;
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if (op > TMaxValue)
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{
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SetFpsrQCFlag(State);
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return TMaxValue;
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}
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else
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{
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return op;
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}
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}
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public static long UnarySignedSatQAbsOrNeg(long op, AThreadState State)
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{
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if (op == long.MinValue)
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{
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SetFpsrQCFlag(State);
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return long.MaxValue;
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}
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else
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{
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return op;
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}
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}
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public static long BinarySignedSatQAdd(long op1, long op2, AThreadState State)
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{
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long Add = op1 + op2;
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if ((~(op1 ^ op2) & (op1 ^ Add)) < 0L)
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{
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SetFpsrQCFlag(State);
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if (op1 < 0L)
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{
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return long.MinValue;
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}
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else
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{
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return long.MaxValue;
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}
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}
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else
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{
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return Add;
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}
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}
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public static ulong BinaryUnsignedSatQAdd(ulong op1, ulong op2, AThreadState State)
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{
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ulong Add = op1 + op2;
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if ((Add < op1) && (Add < op2))
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{
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SetFpsrQCFlag(State);
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return ulong.MaxValue;
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}
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else
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{
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return Add;
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}
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}
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public static long BinarySignedSatQSub(long op1, long op2, AThreadState State)
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{
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long Sub = op1 - op2;
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if (((op1 ^ op2) & (op1 ^ Sub)) < 0L)
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{
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SetFpsrQCFlag(State);
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if (op1 < 0L)
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{
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return long.MinValue;
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}
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else
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{
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return long.MaxValue;
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}
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}
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else
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{
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return Sub;
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}
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}
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public static ulong BinaryUnsignedSatQSub(ulong op1, ulong op2, AThreadState State)
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{
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ulong Sub = op1 - op2;
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if (op1 < op2)
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{
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SetFpsrQCFlag(State);
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return ulong.MinValue;
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}
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else
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{
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return Sub;
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}
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}
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public static long BinarySignedSatQAcc(ulong op1, long op2, AThreadState State)
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{
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if (op1 <= (ulong)long.MaxValue)
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{
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// op1 from ulong.MinValue to (ulong)long.MaxValue
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// op2 from long.MinValue to long.MaxValue
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long Add = (long)op1 + op2;
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if ((~op2 & Add) < 0L)
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{
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SetFpsrQCFlag(State);
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return long.MaxValue;
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}
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else
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{
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return Add;
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}
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}
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else if (op2 >= 0L)
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{
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// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
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// op2 from (long)ulong.MinValue to long.MaxValue
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SetFpsrQCFlag(State);
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return long.MaxValue;
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}
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else
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{
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// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
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// op2 from long.MinValue to (long)ulong.MinValue - 1L
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ulong Add = op1 + (ulong)op2;
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if (Add > (ulong)long.MaxValue)
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{
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SetFpsrQCFlag(State);
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return long.MaxValue;
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}
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else
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{
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return (long)Add;
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}
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}
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}
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public static ulong BinaryUnsignedSatQAcc(long op1, ulong op2, AThreadState State)
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{
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if (op1 >= 0L)
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{
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// op1 from (long)ulong.MinValue to long.MaxValue
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// op2 from ulong.MinValue to ulong.MaxValue
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ulong Add = (ulong)op1 + op2;
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if ((Add < (ulong)op1) && (Add < op2))
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{
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SetFpsrQCFlag(State);
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return ulong.MaxValue;
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}
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else
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{
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return Add;
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}
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}
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else if (op2 > (ulong)long.MaxValue)
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{
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// op1 from long.MinValue to (long)ulong.MinValue - 1L
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// op2 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
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return (ulong)op1 + op2;
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}
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else
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{
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// op1 from long.MinValue to (long)ulong.MinValue - 1L
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// op2 from ulong.MinValue to (ulong)long.MaxValue
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long Add = op1 + (long)op2;
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if (Add < (long)ulong.MinValue)
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{
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SetFpsrQCFlag(State);
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return ulong.MinValue;
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}
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else
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{
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return (ulong)Add;
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}
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}
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}
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private static void SetFpsrQCFlag(AThreadState State)
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{
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const int QCFlagBit = 27;
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State.Fpsr |= 1 << QCFlagBit;
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}
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#endregion
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#region "Count"
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public static ulong CountLeadingSigns(ulong Value, int Size)
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{
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Value ^= Value >> 1;
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int HighBit = Size - 2;
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for (int Bit = HighBit; Bit >= 0; Bit--)
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{
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if (((Value >> Bit) & 0b1) != 0)
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{
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return (ulong)(HighBit - Bit);
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}
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}
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return (ulong)(Size - 1);
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}
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private static readonly byte[] ClzNibbleTbl = { 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
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public static ulong CountLeadingZeros(ulong Value, int Size)
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{
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if (Value == 0)
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{
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return (ulong)Size;
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}
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int NibbleIdx = Size;
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int PreCount, Count = 0;
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do
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{
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NibbleIdx -= 4;
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PreCount = ClzNibbleTbl[(Value >> NibbleIdx) & 0b1111];
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Count += PreCount;
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}
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while (PreCount == 4);
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return (ulong)Count;
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}
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public static uint CountSetBits8(uint Value)
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{
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Value = ((Value >> 1) & 0x55) + (Value & 0x55);
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Value = ((Value >> 2) & 0x33) + (Value & 0x33);
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return (Value >> 4) + (Value & 0x0f);
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}
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#endregion
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#region "Crc32"
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private const uint Crc32RevPoly = 0xedb88320;
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private const uint Crc32cRevPoly = 0x82f63b78;
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public static uint Crc32b(uint Crc, byte Val) => Crc32 (Crc, Crc32RevPoly, Val);
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public static uint Crc32h(uint Crc, ushort Val) => Crc32h(Crc, Crc32RevPoly, Val);
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public static uint Crc32w(uint Crc, uint Val) => Crc32w(Crc, Crc32RevPoly, Val);
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public static uint Crc32x(uint Crc, ulong Val) => Crc32x(Crc, Crc32RevPoly, Val);
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public static uint Crc32cb(uint Crc, byte Val) => Crc32 (Crc, Crc32cRevPoly, Val);
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public static uint Crc32ch(uint Crc, ushort Val) => Crc32h(Crc, Crc32cRevPoly, Val);
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public static uint Crc32cw(uint Crc, uint Val) => Crc32w(Crc, Crc32cRevPoly, Val);
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public static uint Crc32cx(uint Crc, ulong Val) => Crc32x(Crc, Crc32cRevPoly, Val);
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private static uint Crc32h(uint Crc, uint Poly, ushort Val)
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{
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Crc = Crc32(Crc, Poly, (byte)(Val >> 0));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 8));
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return Crc;
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}
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private static uint Crc32w(uint Crc, uint Poly, uint Val)
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{
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Crc = Crc32(Crc, Poly, (byte)(Val >> 0 ));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 8 ));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 16));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 24));
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return Crc;
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}
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private static uint Crc32x(uint Crc, uint Poly, ulong Val)
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{
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Crc = Crc32(Crc, Poly, (byte)(Val >> 0 ));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 8 ));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 16));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 24));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 32));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 40));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 48));
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Crc = Crc32(Crc, Poly, (byte)(Val >> 56));
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return Crc;
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}
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private static uint Crc32(uint Crc, uint Poly, byte Val)
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{
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Crc ^= Val;
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for (int Bit = 7; Bit >= 0; Bit--)
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{
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uint Mask = (uint)(-(int)(Crc & 1));
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Crc = (Crc >> 1) ^ (Poly & Mask);
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}
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return Crc;
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}
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#endregion
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#region "Sha256"
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static Vector128<float> HashLower(Vector128<float> hash_abcd, Vector128<float> hash_efgh, Vector128<float> wk)
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{
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return SHA256hash(hash_abcd, hash_efgh, wk, true);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static Vector128<float> HashUpper(Vector128<float> hash_efgh, Vector128<float> hash_abcd, Vector128<float> wk)
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{
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return SHA256hash(hash_abcd, hash_efgh, wk, false);
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}
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public static Vector128<float> SchedulePart1(Vector128<float> w0_3, Vector128<float> w4_7)
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{
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Vector128<float> result = new Vector128<float>();
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for (int e = 0; e <= 3; e++)
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{
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uint elt = (uint)VectorExtractIntZx(e <= 2 ? w0_3 : w4_7, (byte)(e <= 2 ? e + 1 : 0), 2);
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elt = elt.Ror(7) ^ elt.Ror(18) ^ elt.Lsr(3);
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elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2);
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result = VectorInsertInt((ulong)elt, result, (byte)e, 2);
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}
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return result;
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}
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public static Vector128<float> SchedulePart2(Vector128<float> w0_3, Vector128<float> w8_11, Vector128<float> w12_15)
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{
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Vector128<float> result = new Vector128<float>();
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ulong T1 = VectorExtractIntZx(w12_15, (byte)1, 3);
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for (int e = 0; e <= 1; e++)
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{
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uint elt = T1.ULongPart(e);
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elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10);
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elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2);
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elt += (uint)VectorExtractIntZx(w8_11, (byte)(e + 1), 2);
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result = VectorInsertInt((ulong)elt, result, (byte)e, 2);
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}
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T1 = VectorExtractIntZx(result, (byte)0, 3);
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for (int e = 2; e <= 3; e++)
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{
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uint elt = T1.ULongPart(e - 2);
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elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10);
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elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2);
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elt += (uint)VectorExtractIntZx(e == 2 ? w8_11 : w12_15, (byte)(e == 2 ? 3 : 0), 2);
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result = VectorInsertInt((ulong)elt, result, (byte)e, 2);
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}
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return result;
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}
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private static Vector128<float> SHA256hash(Vector128<float> X, Vector128<float> Y, Vector128<float> W, bool part1)
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{
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for (int e = 0; e <= 3; e++)
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{
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uint chs = SHAchoose((uint)VectorExtractIntZx(Y, (byte)0, 2),
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(uint)VectorExtractIntZx(Y, (byte)1, 2),
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(uint)VectorExtractIntZx(Y, (byte)2, 2));
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uint maj = SHAmajority((uint)VectorExtractIntZx(X, (byte)0, 2),
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(uint)VectorExtractIntZx(X, (byte)1, 2),
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(uint)VectorExtractIntZx(X, (byte)2, 2));
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uint t1 = (uint)VectorExtractIntZx(Y, (byte)3, 2);
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t1 += SHAhashSIGMA1((uint)VectorExtractIntZx(Y, (byte)0, 2)) + chs;
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t1 += (uint)VectorExtractIntZx(W, (byte)e, 2);
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uint t2 = t1 + (uint)VectorExtractIntZx(X, (byte)3, 2);
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X = VectorInsertInt((ulong)t2, X, (byte)3, 2);
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t2 = t1 + SHAhashSIGMA0((uint)VectorExtractIntZx(X, (byte)0, 2)) + maj;
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Y = VectorInsertInt((ulong)t2, Y, (byte)3, 2);
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Rol32_256(ref Y, ref X);
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}
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return part1 ? X : Y;
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}
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private static void Rol32_256(ref Vector128<float> Y, ref Vector128<float> X)
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{
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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uint yE3 = (uint)VectorExtractIntZx(Y, (byte)3, 2);
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uint xE3 = (uint)VectorExtractIntZx(X, (byte)3, 2);
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Y = Sse.StaticCast<uint, float>(Sse2.ShiftLeftLogical128BitLane(Sse.StaticCast<float, uint>(Y), (byte)4));
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X = Sse.StaticCast<uint, float>(Sse2.ShiftLeftLogical128BitLane(Sse.StaticCast<float, uint>(X), (byte)4));
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Y = VectorInsertInt((ulong)xE3, Y, (byte)0, 2);
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X = VectorInsertInt((ulong)yE3, X, (byte)0, 2);
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}
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private static uint SHAhashSIGMA0(uint x)
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{
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return x.Ror(2) ^ x.Ror(13) ^ x.Ror(22);
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}
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private static uint SHAhashSIGMA1(uint x)
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{
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return x.Ror(6) ^ x.Ror(11) ^ x.Ror(25);
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}
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private static uint SHAmajority(uint x, uint y, uint z)
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{
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return (x & y) | ((x | y) & z);
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}
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private static uint SHAchoose(uint x, uint y, uint z)
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{
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|
return ((y ^ z) & x) ^ z;
|
|
}
|
|
|
|
private static uint Ror(this uint value, int count)
|
|
{
|
|
return (value >> count) | (value << (32 - count));
|
|
}
|
|
|
|
private static uint Lsr(this uint value, int count)
|
|
{
|
|
return value >> count;
|
|
}
|
|
|
|
private static uint ULongPart(this ulong value, int part)
|
|
{
|
|
return part == 0
|
|
? (uint)(value & 0xFFFFFFFFUL)
|
|
: (uint)(value >> 32);
|
|
}
|
|
#endregion
|
|
|
|
#region "Reverse"
|
|
public static uint ReverseBits8(uint Value)
|
|
{
|
|
Value = ((Value & 0xaa) >> 1) | ((Value & 0x55) << 1);
|
|
Value = ((Value & 0xcc) >> 2) | ((Value & 0x33) << 2);
|
|
|
|
return (Value >> 4) | ((Value & 0x0f) << 4);
|
|
}
|
|
|
|
public static uint ReverseBits32(uint Value)
|
|
{
|
|
Value = ((Value & 0xaaaaaaaa) >> 1) | ((Value & 0x55555555) << 1);
|
|
Value = ((Value & 0xcccccccc) >> 2) | ((Value & 0x33333333) << 2);
|
|
Value = ((Value & 0xf0f0f0f0) >> 4) | ((Value & 0x0f0f0f0f) << 4);
|
|
Value = ((Value & 0xff00ff00) >> 8) | ((Value & 0x00ff00ff) << 8);
|
|
|
|
return (Value >> 16) | (Value << 16);
|
|
}
|
|
|
|
public static ulong ReverseBits64(ulong Value)
|
|
{
|
|
Value = ((Value & 0xaaaaaaaaaaaaaaaa) >> 1 ) | ((Value & 0x5555555555555555) << 1 );
|
|
Value = ((Value & 0xcccccccccccccccc) >> 2 ) | ((Value & 0x3333333333333333) << 2 );
|
|
Value = ((Value & 0xf0f0f0f0f0f0f0f0) >> 4 ) | ((Value & 0x0f0f0f0f0f0f0f0f) << 4 );
|
|
Value = ((Value & 0xff00ff00ff00ff00) >> 8 ) | ((Value & 0x00ff00ff00ff00ff) << 8 );
|
|
Value = ((Value & 0xffff0000ffff0000) >> 16) | ((Value & 0x0000ffff0000ffff) << 16);
|
|
|
|
return (Value >> 32) | (Value << 32);
|
|
}
|
|
|
|
public static uint ReverseBytes16_32(uint Value) => (uint)ReverseBytes16_64(Value);
|
|
public static uint ReverseBytes32_32(uint Value) => (uint)ReverseBytes32_64(Value);
|
|
|
|
public static ulong ReverseBytes16_64(ulong Value) => ReverseBytes(Value, RevSize.Rev16);
|
|
public static ulong ReverseBytes32_64(ulong Value) => ReverseBytes(Value, RevSize.Rev32);
|
|
public static ulong ReverseBytes64(ulong Value) => ReverseBytes(Value, RevSize.Rev64);
|
|
|
|
private enum RevSize
|
|
{
|
|
Rev16,
|
|
Rev32,
|
|
Rev64
|
|
}
|
|
|
|
private static ulong ReverseBytes(ulong Value, RevSize Size)
|
|
{
|
|
Value = ((Value & 0xff00ff00ff00ff00) >> 8) | ((Value & 0x00ff00ff00ff00ff) << 8);
|
|
|
|
if (Size == RevSize.Rev16)
|
|
{
|
|
return Value;
|
|
}
|
|
|
|
Value = ((Value & 0xffff0000ffff0000) >> 16) | ((Value & 0x0000ffff0000ffff) << 16);
|
|
|
|
if (Size == RevSize.Rev32)
|
|
{
|
|
return Value;
|
|
}
|
|
|
|
Value = ((Value & 0xffffffff00000000) >> 32) | ((Value & 0x00000000ffffffff) << 32);
|
|
|
|
if (Size == RevSize.Rev64)
|
|
{
|
|
return Value;
|
|
}
|
|
|
|
throw new ArgumentException(nameof(Size));
|
|
}
|
|
#endregion
|
|
|
|
#region "MultiplyHigh"
|
|
public static long SMulHi128(long LHS, long RHS)
|
|
{
|
|
long Result = (long)UMulHi128((ulong)LHS, (ulong)RHS);
|
|
if (LHS < 0) Result -= RHS;
|
|
if (RHS < 0) Result -= LHS;
|
|
|
|
return Result;
|
|
}
|
|
|
|
public static ulong UMulHi128(ulong LHS, ulong RHS)
|
|
{
|
|
//long multiplication
|
|
//multiply 32 bits at a time in 64 bit, the result is what's carried over 64 bits.
|
|
ulong LHigh = LHS >> 32;
|
|
ulong LLow = LHS & 0xFFFFFFFF;
|
|
ulong RHigh = RHS >> 32;
|
|
ulong RLow = RHS & 0xFFFFFFFF;
|
|
ulong Z2 = LLow * RLow;
|
|
ulong T = LHigh * RLow + (Z2 >> 32);
|
|
ulong Z1 = T & 0xFFFFFFFF;
|
|
ulong Z0 = T >> 32;
|
|
Z1 += LLow * RHigh;
|
|
|
|
return LHigh * RHigh + Z0 + (Z1 >> 32);
|
|
}
|
|
#endregion
|
|
}
|
|
}
|