a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
135 lines
3.6 KiB
C#
135 lines
3.6 KiB
C#
using ARMeilleure.CodeGen;
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using ARMeilleure.Memory;
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using System;
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using System.Collections.Generic;
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using System.Runtime.InteropServices;
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namespace ARMeilleure.Translation
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{
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static class JitCache
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{
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private const int PageSize = 4 * 1024;
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private const int PageMask = PageSize - 1;
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private const int CodeAlignment = 4; // Bytes
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private const int CacheSize = 512 * 1024 * 1024;
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private static IntPtr _basePointer;
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private static int _offset;
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private static List<JitCacheEntry> _cacheEntries;
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private static object _lock;
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static JitCache()
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{
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_basePointer = MemoryManagement.Allocate(CacheSize);
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if (RuntimeInformation.IsOSPlatform(OSPlatform.Windows))
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{
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JitUnwindWindows.InstallFunctionTableHandler(_basePointer, CacheSize);
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// The first page is used for the table based SEH structs.
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_offset = PageSize;
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}
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_cacheEntries = new List<JitCacheEntry>();
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_lock = new object();
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}
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public static IntPtr Map(CompiledFunction func)
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{
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byte[] code = func.Code;
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lock (_lock)
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{
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int funcOffset = Allocate(code.Length);
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IntPtr funcPtr = _basePointer + funcOffset;
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Marshal.Copy(code, 0, funcPtr, code.Length);
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ReprotectRange(funcOffset, code.Length);
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Add(new JitCacheEntry(funcOffset, code.Length, func.UnwindInfo));
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return funcPtr;
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}
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}
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private static void ReprotectRange(int offset, int size)
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{
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// Map pages that are already full as RX.
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// Map pages that are not full yet as RWX.
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// On unix, the address must be page aligned.
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int endOffs = offset + size;
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int pageStart = offset & ~PageMask;
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int pageEnd = endOffs & ~PageMask;
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int fullPagesSize = pageEnd - pageStart;
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if (fullPagesSize != 0)
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{
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IntPtr funcPtr = _basePointer + pageStart;
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MemoryManagement.Reprotect(funcPtr, (ulong)fullPagesSize, MemoryProtection.ReadAndExecute);
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}
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int remaining = endOffs - pageEnd;
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if (remaining != 0)
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{
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IntPtr funcPtr = _basePointer + pageEnd;
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MemoryManagement.Reprotect(funcPtr, (ulong)remaining, MemoryProtection.ReadWriteExecute);
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}
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}
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private static int Allocate(int codeSize)
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{
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codeSize = checked(codeSize + (CodeAlignment - 1)) & ~(CodeAlignment - 1);
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int allocOffset = _offset;
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_offset += codeSize;
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if ((ulong)(uint)_offset > CacheSize)
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{
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throw new OutOfMemoryException();
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}
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return allocOffset;
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}
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private static void Add(JitCacheEntry entry)
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{
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_cacheEntries.Add(entry);
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}
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public static bool TryFind(int offset, out JitCacheEntry entry)
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{
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lock (_lock)
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{
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foreach (JitCacheEntry cacheEntry in _cacheEntries)
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{
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int endOffset = cacheEntry.Offset + cacheEntry.Size;
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if (offset >= cacheEntry.Offset && offset < endOffset)
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{
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entry = cacheEntry;
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return true;
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}
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}
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}
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entry = default(JitCacheEntry);
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return false;
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}
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}
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} |