a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
34 lines
1.6 KiB
C#
34 lines
1.6 KiB
C#
// ReSharper disable InconsistentNaming
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namespace Ryujinx.Tests.Unicorn.Native
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{
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public enum UnicornMode : uint
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{
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UC_MODE_LITTLE_ENDIAN = 0, // little-endian mode (default mode)
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UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
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// arm / arm64
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UC_MODE_ARM = 0, // ARM mode
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UC_MODE_THUMB = 1 << 4, // THUMB mode (including Thumb-2)
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UC_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series (currently unsupported)
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UC_MODE_V8 = 1 << 6, // ARMv8 A32 encodings for ARM (currently unsupported)
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// mips
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UC_MODE_MICRO = 1 << 4, // MicroMips mode (currently unsupported)
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UC_MODE_MIPS3 = 1 << 5, // Mips III ISA (currently unsupported)
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UC_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA (currently unsupported)
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UC_MODE_MIPS32 = 1 << 2, // Mips32 ISA
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UC_MODE_MIPS64 = 1 << 3, // Mips64 ISA
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// x86 / x64
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UC_MODE_16 = 1 << 1, // 16-bit mode
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UC_MODE_32 = 1 << 2, // 32-bit mode
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UC_MODE_64 = 1 << 3, // 64-bit mode
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// ppc
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UC_MODE_PPC32 = 1 << 2, // 32-bit mode (currently unsupported)
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UC_MODE_PPC64 = 1 << 3, // 64-bit mode (currently unsupported)
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UC_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode (currently unsupported)
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// sparc
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UC_MODE_SPARC32 = 1 << 2, // 32-bit mode
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UC_MODE_SPARC64 = 1 << 3, // 64-bit mode
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UC_MODE_V9 = 1 << 4, // SparcV9 mode (currently unsupported)
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// m68k
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}
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}
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