gdkchan a1efd87c45 Implement remaining Arm64 HINT instructions as NOP (#4658) ... * Implement remaining HINT instructions as NOP * Split HINT encodings more to account for CSDB		2023-04-09 13:21:16 -03:00
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Optimizations
Block.cs
Condition.cs
DataOp.cs
Decoder.cs
DecoderHelper.cs
DecoderMode.cs
InstDescriptor.cs
InstEmitter.cs
IntType.cs
IOpCode.cs
IOpCode32.cs
IOpCode32Adr.cs
IOpCode32Alu.cs
IOpCode32AluBf.cs
IOpCode32AluImm.cs
IOpCode32AluImm16.cs
IOpCode32AluMla.cs
IOpCode32AluReg.cs
IOpCode32AluRsImm.cs
IOpCode32AluRsReg.cs
IOpCode32AluUmull.cs
IOpCode32AluUx.cs
IOpCode32BImm.cs
IOpCode32BReg.cs
IOpCode32Exception.cs
IOpCode32HasSetFlags.cs
IOpCode32Mem.cs
IOpCode32MemEx.cs
IOpCode32MemMult.cs
IOpCode32MemReg.cs
IOpCode32MemRsImm.cs
IOpCode32Simd.cs
IOpCode32SimdImm.cs
IOpCodeAlu.cs
IOpCodeAluImm.cs
IOpCodeAluRs.cs
IOpCodeAluRx.cs
IOpCodeBImm.cs
IOpCodeCond.cs
IOpCodeLit.cs
IOpCodeSimd.cs
OpCode.cs
OpCode32.cs
OpCode32Alu.cs
OpCode32AluBf.cs
OpCode32AluImm.cs
OpCode32AluImm16.cs
OpCode32AluMla.cs
OpCode32AluReg.cs
OpCode32AluRsImm.cs
OpCode32AluRsReg.cs
OpCode32AluUmull.cs
OpCode32AluUx.cs
OpCode32BImm.cs
OpCode32BReg.cs
OpCode32Exception.cs
OpCode32Mem.cs
OpCode32MemImm.cs
OpCode32MemImm8.cs
OpCode32MemLdEx.cs
OpCode32MemMult.cs
OpCode32MemReg.cs
OpCode32MemRsImm.cs
OpCode32MemStEx.cs
OpCode32Mrs.cs
OpCode32MsrReg.cs
OpCode32Sat.cs
OpCode32Sat16.cs
OpCode32Simd.cs
OpCode32SimdBase.cs
OpCode32SimdBinary.cs
OpCode32SimdCmpZ.cs
OpCode32SimdCvtFI.cs
OpCode32SimdCvtTB.cs
OpCode32SimdDupElem.cs
OpCode32SimdDupGP.cs
OpCode32SimdExt.cs
OpCode32SimdImm.cs
OpCode32SimdImm44.cs
OpCode32SimdLong.cs
OpCode32SimdMemImm.cs
OpCode32SimdMemMult.cs
OpCode32SimdMemPair.cs
OpCode32SimdMemSingle.cs
OpCode32SimdMovGp.cs
OpCode32SimdMovGpDouble.cs
OpCode32SimdMovGpElem.cs
OpCode32SimdMovn.cs
OpCode32SimdReg.cs
OpCode32SimdRegElem.cs
OpCode32SimdRegElemLong.cs
OpCode32SimdRegLong.cs
OpCode32SimdRegS.cs
OpCode32SimdRegWide.cs
OpCode32SimdRev.cs
OpCode32SimdS.cs
OpCode32SimdSel.cs
OpCode32SimdShImm.cs
OpCode32SimdShImmLong.cs
OpCode32SimdShImmNarrow.cs
OpCode32SimdSpecial.cs
OpCode32SimdSqrte.cs
OpCode32SimdTbl.cs
OpCode32System.cs
OpCodeAdr.cs
OpCodeAlu.cs
OpCodeAluBinary.cs
OpCodeAluImm.cs
OpCodeAluRs.cs
OpCodeAluRx.cs
OpCodeBfm.cs
OpCodeBImm.cs
OpCodeBImmAl.cs
OpCodeBImmCmp.cs
OpCodeBImmCond.cs
OpCodeBImmTest.cs
OpCodeBReg.cs
OpCodeCcmp.cs
OpCodeCcmpImm.cs
OpCodeCcmpReg.cs
OpCodeCsel.cs
OpCodeException.cs
OpCodeMem.cs
OpCodeMemEx.cs
OpCodeMemImm.cs
OpCodeMemLit.cs
OpCodeMemPair.cs
OpCodeMemReg.cs
OpCodeMov.cs
OpCodeMul.cs
OpCodeSimd.cs
OpCodeSimdCvt.cs
OpCodeSimdExt.cs
OpCodeSimdFcond.cs
OpCodeSimdFmov.cs
OpCodeSimdHelper.cs
OpCodeSimdImm.cs
OpCodeSimdIns.cs
OpCodeSimdMemImm.cs
OpCodeSimdMemLit.cs
OpCodeSimdMemMs.cs
OpCodeSimdMemPair.cs
OpCodeSimdMemReg.cs
OpCodeSimdMemSs.cs
OpCodeSimdReg.cs
OpCodeSimdRegElem.cs
OpCodeSimdRegElemF.cs
OpCodeSimdShImm.cs
OpCodeSimdTbl.cs
OpCodeSystem.cs
OpCodeT16.cs
OpCodeT16AddSubImm3.cs
OpCodeT16AddSubReg.cs
OpCodeT16AddSubSp.cs
OpCodeT16Adr.cs
OpCodeT16AluImm8.cs
OpCodeT16AluImmZero.cs
OpCodeT16AluRegHigh.cs
OpCodeT16AluRegLow.cs
OpCodeT16AluUx.cs
OpCodeT16BImm8.cs
OpCodeT16BImm11.cs
OpCodeT16BImmCmp.cs
OpCodeT16BReg.cs
OpCodeT16Exception.cs
OpCodeT16IfThen.cs
OpCodeT16MemImm5.cs
OpCodeT16MemLit.cs
OpCodeT16MemMult.cs
OpCodeT16MemReg.cs
OpCodeT16MemSp.cs
OpCodeT16MemStack.cs
OpCodeT16ShiftImm.cs
OpCodeT16ShiftReg.cs
OpCodeT16SpRel.cs
OpCodeT32.cs
OpCodeT32Alu.cs
OpCodeT32AluBf.cs
OpCodeT32AluImm.cs
OpCodeT32AluImm12.cs
OpCodeT32AluMla.cs
OpCodeT32AluReg.cs
OpCodeT32AluRsImm.cs
OpCodeT32AluUmull.cs
OpCodeT32AluUx.cs
OpCodeT32BImm20.cs
OpCodeT32BImm24.cs
OpCodeT32MemImm8.cs
OpCodeT32MemImm8D.cs
OpCodeT32MemImm12.cs
OpCodeT32MemLdEx.cs
OpCodeT32MemMult.cs
OpCodeT32MemRsImm.cs
OpCodeT32MemStEx.cs
OpCodeT32MovImm16.cs
OpCodeT32ShiftReg.cs
OpCodeT32Tb.cs
OpCodeTable.cs	Implement remaining Arm64 HINT instructions as NOP (#4658)	2023-04-09 13:21:16 -03:00
RegisterSize.cs
ShiftType.cs