ca1e37a295
* Delete Bits.cs * Delete Integer.cs * Delete Instructions.cs * Delete Pseudocode.cs * Add files via upload * Add mnemonic. * Literals all uppercase. * Nit. * Allow FPSR control. * Allow FPSR control. * Allow FPSR control.
44 lines
1.8 KiB
C#
44 lines
1.8 KiB
C#
using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestSimdCvt : CpuTest
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{
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[TestCase((ushort)0x0000, 0x00000000u)] // Positive Zero
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[TestCase((ushort)0x8000, 0x80000000u)] // Negative Zero
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[TestCase((ushort)0x3E00, 0x3FC00000u)] // +1.5
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[TestCase((ushort)0xBE00, 0xBFC00000u)] // -1.5
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[TestCase((ushort)0xFFFF, 0xFFFFE000u)] // -QNaN
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[TestCase((ushort)0x7C00, 0x7F800000u)] // +Inf
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[TestCase((ushort)0x3C00, 0x3F800000u)] // 1.0
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[TestCase((ushort)0x3C01, 0x3F802000u)] // 1.0009765625
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[TestCase((ushort)0xC000, 0xC0000000u)] // -2.0
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[TestCase((ushort)0x7BFF, 0x477FE000u)] // 65504.0 (Largest Normal)
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[TestCase((ushort)0x03FF, 0x387FC000u)] // 0.00006097555 (Largest Subnormal)
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[TestCase((ushort)0x0001, 0x33800000u)] // 5.96046448e-8 (Smallest Subnormal)
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public void Fcvtl_V_f16(ushort Value, uint Result)
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{
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uint Opcode = 0x0E217801; // FCVTL V1.4S, V0.4H
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Vector128<float> V0 = Sse.StaticCast<ushort, float>(Sse2.SetAllVector128(Value));
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0);
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Assert.Multiple(() =>
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{
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Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)0), Is.EqualTo(Result));
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Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)1), Is.EqualTo(Result));
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Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)2), Is.EqualTo(Result));
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Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)3), Is.EqualTo(Result));
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});
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CompareAgainstUnicorn();
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}
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}
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}
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