509 lines
16 KiB
C#
509 lines
16 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitMemoryHelper
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{
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private enum Extension
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{
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Zx,
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Sx32,
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Sx64
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}
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public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Zx, rt, size);
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}
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public static void EmitLoadSx32(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Sx32, rt, size);
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}
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public static void EmitLoadSx64(ArmEmitterContext context, Operand address, int rt, int size)
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{
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EmitLoad(context, address, Extension.Sx64, rt, size);
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}
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private static void EmitLoad(ArmEmitterContext context, Operand address, Extension ext, int rt, int size)
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{
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bool isSimd = IsSimd(context);
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if ((uint)size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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EmitReadVector(context, address, context.VectorZero(), rt, 0, size);
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}
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else
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{
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EmitReadInt(context, address, rt, size);
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}
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if (!isSimd)
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{
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Operand value = GetIntOrZR(context, rt);
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if (ext == Extension.Sx32 || ext == Extension.Sx64)
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{
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OperandType destType = ext == Extension.Sx64 ? OperandType.I64 : OperandType.I32;
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switch (size)
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{
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case 0: value = context.SignExtend8 (destType, value); break;
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case 1: value = context.SignExtend16(destType, value); break;
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case 2: value = context.SignExtend32(destType, value); break;
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}
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}
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SetIntOrZR(context, rt, value);
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}
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}
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public static void EmitLoadSimd(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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EmitReadVector(context, address, vector, rt, elem, size);
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}
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public static void EmitStore(ArmEmitterContext context, Operand address, int rt, int size)
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{
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bool isSimd = IsSimd(context);
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if ((uint)size > (isSimd ? 4 : 3))
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{
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throw new ArgumentOutOfRangeException(nameof(size));
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}
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if (isSimd)
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{
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EmitWriteVector(context, address, rt, 0, size);
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}
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else
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{
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EmitWriteInt(context, address, rt, size);
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}
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}
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public static void EmitStoreSimd(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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EmitWriteVector(context, address, rt, elem, size);
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}
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private static bool IsSimd(ArmEmitterContext context)
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{
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return context.CurrOp is IOpCodeSimd &&
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!(context.CurrOp is OpCodeSimdMemMs ||
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context.CurrOp is OpCodeSimdMemSs);
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}
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private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitReadIntFallback(context, address, rt, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = null;
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switch (size)
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{
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case 0:
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value = context.Load8(physAddr);
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break;
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case 1:
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value = context.Load16(physAddr);
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break;
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case 2:
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value = context.Load(OperandType.I32, physAddr);
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break;
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case 3:
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value = context.Load(OperandType.I64, physAddr);
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break;
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}
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SetInt(context, rt, value);
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context.MarkLabel(lblEnd);
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}
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private static void EmitReadVector(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitReadVectorFallback(context, address, vector, rt, elem, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = null;
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switch (size)
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{
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case 0:
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value = context.VectorInsert8(vector, context.Load8(physAddr), elem);
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break;
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case 1:
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value = context.VectorInsert16(vector, context.Load16(physAddr), elem);
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break;
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case 2:
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value = context.VectorInsert(vector, context.Load(OperandType.I32, physAddr), elem);
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break;
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case 3:
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value = context.VectorInsert(vector, context.Load(OperandType.I64, physAddr), elem);
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break;
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case 4:
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value = context.Load(OperandType.V128, physAddr);
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break;
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}
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context.Copy(GetVec(rt), value);
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context.MarkLabel(lblEnd);
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}
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private static Operand VectorCreate(ArmEmitterContext context, Operand value)
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{
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return context.VectorInsert(context.VectorZero(), value, 0);
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}
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private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitWriteIntFallback(context, address, rt, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = GetInt(context, rt);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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switch (size)
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{
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case 0: context.Store8 (physAddr, value); break;
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case 1: context.Store16(physAddr, value); break;
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case 2: context.Store (physAddr, value); break;
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case 3: context.Store (physAddr, value); break;
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}
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context.MarkLabel(lblEnd);
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}
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private static void EmitWriteVector(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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Operand isUnalignedAddr = EmitAddressCheck(context, address, size);
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Operand lblFastPath = Label();
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Operand lblSlowPath = Label();
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Operand lblEnd = Label();
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context.BranchIfFalse(lblFastPath, isUnalignedAddr);
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context.MarkLabel(lblSlowPath);
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EmitWriteVectorFallback(context, address, rt, elem, size);
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context.Branch(lblEnd);
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context.MarkLabel(lblFastPath);
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Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath);
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Operand value = GetVec(rt);
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switch (size)
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{
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case 0:
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context.Store8(physAddr, context.VectorExtract8(value, elem));
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break;
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case 1:
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context.Store16(physAddr, context.VectorExtract16(value, elem));
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break;
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case 2:
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context.Store(physAddr, context.VectorExtract(OperandType.FP32, value, elem));
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break;
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case 3:
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context.Store(physAddr, context.VectorExtract(OperandType.FP64, value, elem));
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break;
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case 4:
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context.Store(physAddr, value);
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break;
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}
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context.MarkLabel(lblEnd);
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}
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private static Operand EmitAddressCheck(ArmEmitterContext context, Operand address, int size)
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{
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long addressCheckMask = ~(context.Memory.AddressSpaceSize - 1);
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addressCheckMask |= (1u << size) - 1;
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return context.BitwiseAnd(address, Const(address.Type, addressCheckMask));
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}
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private static Operand EmitPtPointerLoad(ArmEmitterContext context, Operand address, Operand lblFallbackPath)
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{
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Operand pte = Const(context.Memory.PageTable.ToInt64());
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int bit = MemoryManager.PageBits;
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do
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{
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Operand addrPart = context.ShiftRightUI(address, Const(bit));
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bit += context.Memory.PtLevelBits;
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if (bit < context.Memory.AddressSpaceBits)
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{
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addrPart = context.BitwiseAnd(addrPart, Const(addrPart.Type, context.Memory.PtLevelMask));
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}
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Operand pteOffset = context.ShiftLeft(addrPart, Const(3));
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if (pteOffset.Type == OperandType.I32)
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{
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pteOffset = context.ZeroExtend32(OperandType.I64, pteOffset);
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}
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Operand pteAddress = context.Add(pte, pteOffset);
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pte = context.Load(OperandType.I64, pteAddress);
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}
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while (bit < context.Memory.AddressSpaceBits);
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Operand hasFlagSet = context.BitwiseAnd(pte, Const((long)MemoryManager.PteFlagsMask));
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context.BranchIfTrue(lblFallbackPath, hasFlagSet);
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Operand pageOffset = context.BitwiseAnd(address, Const(address.Type, MemoryManager.PageMask));
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if (pageOffset.Type == OperandType.I32)
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{
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pageOffset = context.ZeroExtend32(OperandType.I64, pageOffset);
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}
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Operand physAddr = context.Add(pte, pageOffset);
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return physAddr;
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}
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private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
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case 1: fallbackMethodDlg = new _U16_U64(NativeInterface.ReadUInt16); break;
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case 2: fallbackMethodDlg = new _U32_U64(NativeInterface.ReadUInt32); break;
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case 3: fallbackMethodDlg = new _U64_U64(NativeInterface.ReadUInt64); break;
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}
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SetInt(context, rt, context.Call(fallbackMethodDlg, address));
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}
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private static void EmitReadVectorFallback(
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ArmEmitterContext context,
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Operand address,
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Operand vector,
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int rt,
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int elem,
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int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _U8_U64 (NativeInterface.ReadByte); break;
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case 1: fallbackMethodDlg = new _U16_U64 (NativeInterface.ReadUInt16); break;
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case 2: fallbackMethodDlg = new _U32_U64 (NativeInterface.ReadUInt32); break;
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case 3: fallbackMethodDlg = new _U64_U64 (NativeInterface.ReadUInt64); break;
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case 4: fallbackMethodDlg = new _V128_U64(NativeInterface.ReadVector128); break;
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}
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Operand value = context.Call(fallbackMethodDlg, address);
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switch (size)
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{
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case 0: value = context.VectorInsert8 (vector, value, elem); break;
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case 1: value = context.VectorInsert16(vector, value, elem); break;
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case 2: value = context.VectorInsert (vector, value, elem); break;
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case 3: value = context.VectorInsert (vector, value, elem); break;
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}
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context.Copy(GetVec(rt), value);
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}
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private static void EmitWriteIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
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case 1: fallbackMethodDlg = new _Void_U64_U16(NativeInterface.WriteUInt16); break;
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case 2: fallbackMethodDlg = new _Void_U64_U32(NativeInterface.WriteUInt32); break;
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case 3: fallbackMethodDlg = new _Void_U64_U64(NativeInterface.WriteUInt64); break;
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}
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Operand value = GetInt(context, rt);
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if (size < 3 && value.Type == OperandType.I64)
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{
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value = context.ConvertI64ToI32(value);
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}
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context.Call(fallbackMethodDlg, address, value);
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}
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private static void EmitWriteVectorFallback(
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ArmEmitterContext context,
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Operand address,
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int rt,
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int elem,
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int size)
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{
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Delegate fallbackMethodDlg = null;
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switch (size)
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{
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case 0: fallbackMethodDlg = new _Void_U64_U8 (NativeInterface.WriteByte); break;
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case 1: fallbackMethodDlg = new _Void_U64_U16 (NativeInterface.WriteUInt16); break;
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case 2: fallbackMethodDlg = new _Void_U64_U32 (NativeInterface.WriteUInt32); break;
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case 3: fallbackMethodDlg = new _Void_U64_U64 (NativeInterface.WriteUInt64); break;
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case 4: fallbackMethodDlg = new _Void_U64_V128(NativeInterface.WriteVector128); break;
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}
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Operand value = null;
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if (size < 4)
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{
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switch (size)
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{
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case 0:
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value = context.VectorExtract8(GetVec(rt), elem);
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break;
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case 1:
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value = context.VectorExtract16(GetVec(rt), elem);
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break;
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case 2:
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value = context.VectorExtract(OperandType.I32, GetVec(rt), elem);
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break;
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case 3:
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value = context.VectorExtract(OperandType.I64, GetVec(rt), elem);
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break;
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}
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}
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else
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{
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value = GetVec(rt);
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}
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context.Call(fallbackMethodDlg, address, value);
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}
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private static Operand GetInt(ArmEmitterContext context, int rt)
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{
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return context.CurrOp is OpCode32 ? GetIntA32(context, rt) : GetIntOrZR(context, rt);
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}
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private static void SetInt(ArmEmitterContext context, int rt, Operand value)
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{
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if (context.CurrOp is OpCode32)
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{
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SetIntA32(context, rt, value);
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}
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else
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{
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SetIntOrZR(context, rt, value);
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}
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}
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}
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} |